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AMD hudson and yangtze boards: Let mainboard declare power button 

The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and
always had the wake source declared as GPE3. This is not the correct
wake source for all boards. On some laptops declaring a wake source is
not needed, as the wake mechanism is handled by the EC.

Move the declaration of the power button to mainboard ASL files, and
scope it as \_SB.PWRB . This also makes the naming consistent with the
examples in the ACPI spec. The wake source for the PWRB of HP Pavilion
M6 1035dx is removed, as it is incorrect.

Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5546
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2014-04-18 01:42:19 -05:00
parent ce7a8024ff
commit 44f2fab89a
13 changed files with 64 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/amd/olivehill/acpi/gpe.asl
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@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */ /* General event 3 */
Method(_L03) { Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */ /* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Legacy PM event */ /* Legacy PM event */
@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* ExtEvent0 SCI event */ /* ExtEvent0 SCI event */
@ -66,13 +66,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Azalia SCI event */ /* Azalia SCI event */
Method(_L1B) { Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */ /* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

7
src/mainboard/amd/olivehill/dsdt.asl
View File

@ -56,6 +56,13 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl" #include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
Device(PCI0) { Device(PCI0) {
/* Describe the AMD Northbridge */ /* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>

8
src/mainboard/amd/parmer/acpi/gpe.asl
View File

@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */ /* General event 3 */
Method(_L03) { Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */ /* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Legacy PM event */ /* Legacy PM event */
@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* ExtEvent0 SCI event */ /* ExtEvent0 SCI event */
@ -67,13 +67,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Azalia SCI event */ /* Azalia SCI event */
Method(_L1B) { Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */ /* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

7
src/mainboard/amd/parmer/dsdt.asl
View File

@ -55,6 +55,13 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl" #include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
Device(PCI0) { Device(PCI0) {
/* Describe the AMD Northbridge */ /* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>

8
src/mainboard/amd/thatcher/acpi/gpe.asl
View File

@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */ /* General event 3 */
Method(_L03) { Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */ /* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Legacy PM event */ /* Legacy PM event */
@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* ExtEvent0 SCI event */ /* ExtEvent0 SCI event */
@ -67,13 +67,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Azalia SCI event */ /* Azalia SCI event */
Method(_L1B) { Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */ /* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

7
src/mainboard/amd/thatcher/dsdt.asl
View File

@ -55,6 +55,13 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl" #include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
Device(PCI0) { Device(PCI0) {
/* Describe the AMD Northbridge */ /* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>

8
src/mainboard/asrock/imb-a180/acpi/gpe.asl
View File

@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */ /* General event 3 */
Method(_L03) { Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */ /* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Legacy PM event */ /* Legacy PM event */
@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* ExtEvent0 SCI event */ /* ExtEvent0 SCI event */
@ -66,13 +66,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Azalia SCI event */ /* Azalia SCI event */
Method(_L1B) { Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */ /* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

7
src/mainboard/asrock/imb-a180/dsdt.asl
View File

@ -56,6 +56,13 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl" #include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
Device(PCI0) { Device(PCI0) {
/* Describe the AMD Northbridge */ /* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>

8
src/mainboard/asus/f2a85-m/acpi/gpe.asl
View File

@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */ /* General event 3 */
Method(_L03) { Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */ /* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Legacy PM event */ /* Legacy PM event */
@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* ExtEvent0 SCI event */ /* ExtEvent0 SCI event */
@ -64,13 +64,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Method(_L18) { Method(_L18) {
/* DBGO("\\_GPE\\_L18\n") */ /* DBGO("\\_GPE\\_L18\n") */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Azalia SCI event */ /* Azalia SCI event */
Method(_L1B) { Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */ /* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

7
src/mainboard/asus/f2a85-m/dsdt.asl
View File

@ -55,6 +55,13 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl" #include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
Device(PCI0) { Device(PCI0) {
/* Describe the AMD Northbridge */ /* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>

6
src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl
View File

@ -40,7 +40,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* ExtEvent0 SCI event */ /* ExtEvent0 SCI event */
@ -70,13 +70,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
/* Azalia SCI event */ /* Azalia SCI event */
Method(_L1B) { Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */ /* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

6
src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl
View File

@ -98,6 +98,12 @@ Scope (\_SB) {
} }
} }
Device(PWRB) {
Name(_HID, EisaId("PNP0C0C"))
Name(_UID, 0xAA)
Name(_STA, 0x0B)
}
Device (MB) { Device (MB) {
/* Lid open */ /* Lid open */
Method (LIDO) { /* Stub */ } Method (LIDO) { /* Stub */ }

7
src/southbridge/amd/agesa/hudson/acpi/fch.asl
View File

@ -204,10 +204,3 @@ Method(CkOT, 0){
} }
Return(OSTP) Return(OSTP)
} }
Device(PWRB) { /* Start Power button device */
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
Name(_STA, 0x0B) /* sata is invisible */
}