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tegra132: fix Rx FIFO underruns with slower SPI clock 

The SPI controller operates on packets which can be variable
length up to 32-bit packets. It also has the ability to be
put in packed or unpacked mode w.r.t each packet. i.e. does
a single fifo register hold >= 1 packet. The current programming
uses 8-bit packets in unpacked mode which means 4 fifo slots
are used for a 32-bit DMA transfter. As the AHB can only operate
on a minimum of 32-bit bursts the triggers need to be programmed
correctly so that there is room for a full 32-bit DMA transaction.

Previously faster SPI clocks just made things magically work.

BUG=chrome-os-partner:30779
BRANCH=None
TEST=Built and booted through coreboot with 20MHz SPI clock.

Original-Change-Id: I3f1cd4dddcea9514327b2363ed450a527db7e1fe
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208862
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit d9864228a2479e412d7e0d2221fe536f78329acd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I61c145f35e1f889d4f83f3dfea049bfd347c1196
Reviewed-on: http://review.coreboot.org/8649
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2014-07-21 22:11:29 -05:00 committed by Marc Jones
parent 7ddb5f76fe
commit 44f465d21c
1 changed files with 16 additions and 2 deletions
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18
src/soc/nvidia/tegra132/spi.c
View File

@ -530,10 +530,24 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi)
*/ */
setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
if (spi->dma_out) /*
* The DMA triggers have units of packets. As each packet is currently
* 1 byte the triggers need to be set to 4 packets (0b01) to match
* the AHB 32-bit (4 byte) tranfser. Otherwise the FIFO errors can
* occur.
*/
if (spi->dma_out) {
clrsetbits_le32(&spi->regs->dma_ctl,
SPI_DMA_CTL_TX_TRIG_MASK << SPI_DMA_CTL_TX_TRIG_SHIFT,
1 << SPI_DMA_CTL_TX_TRIG_SHIFT);
setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
if (spi->dma_in) }
if (spi->dma_in) {
clrsetbits_le32(&spi->regs->dma_ctl,
SPI_DMA_CTL_RX_TRIG_MASK << SPI_DMA_CTL_RX_TRIG_SHIFT,
1 << SPI_DMA_CTL_RX_TRIG_SHIFT);
setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
}
/* /*
* To avoid underrun conditions, enable APB DMA before SPI DMA for * To avoid underrun conditions, enable APB DMA before SPI DMA for