diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c index 702cd6e4d2..d8d02f22c8 100644 --- a/payloads/libpayload/drivers/udc/chipidea.c +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -81,7 +81,7 @@ static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg, memcpy(&this->device_descriptor, dd, sizeof(*dd)); if (p->qhlist == NULL) - die("failed to allocate memory for usb device mode"); + die("failed to allocate memory for USB device mode"); memset(p->qhlist, 0, sizeof(struct qh) * CI_QHELEMENTS); @@ -102,7 +102,7 @@ static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg, p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS; do { - debug("waiting for usb phy clk valid: %x\n", + debug("waiting for USB phy clk valid: %x\n", readl(&p->opreg->susp_ctrl)); mdelay(1); } while ((readl(&p->opreg->susp_ctrl) & (1 << 7)) == 0); diff --git a/payloads/libpayload/drivers/udc/chipidea_priv.h b/payloads/libpayload/drivers/udc/chipidea_priv.h index ede97ab264..82870c3579 100644 --- a/payloads/libpayload/drivers/udc/chipidea_priv.h +++ b/payloads/libpayload/drivers/udc/chipidea_priv.h @@ -47,7 +47,7 @@ struct chipidea_opreg { uint32_t portsc; // 0x174 uint32_t pad178[15]; uint32_t devlc; // 0x1b4 - /* 25:26: host-desired usb version + /* 25:26: host-desired USB version * 23: force full speed */ uint32_t pad1b8[16]; uint32_t usbmode; // 0x1f8 diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 1cfa8bb6d6..bf8a5eaa81 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -291,7 +291,7 @@ static int ehci_set_async_schedule(ehci_t *ehcic, int enable) /* Memory barrier to ensure that all memory accesses before we set the * async schedule are complete. It was observed especially in the case of - * arm64, that netboot and usb stuff resulted in lots of errors possibly + * arm64, that netboot and USB stuff resulted in lots of errors possibly * due to CPU reordering. Hence, enforcing strict CPU ordering. */ mb(); diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index d98fd9e2bc..942e1b1f6b 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -634,14 +634,14 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr) /* * Should be called by the hub drivers whenever a physical detach occurs - * and can be called by usb class drivers if they are unsatisfied with a + * and can be called by USB class drivers if they are unsatisfied with a * malfunctioning device. */ void usb_detach_device(hci_t *controller, int devno) { /* check if device exists, as we may have - been called yet by the usb class driver */ + been called yet by the USB class driver */ if (controller->devices[devno]) { controller->devices[devno]->destroy (controller->devices[devno]); diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 50fd24b1f8..ed7ad1acd4 100755 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -126,7 +126,7 @@ enum { * MSC commands can be * successful, * fail with proper response or - * fail totally, which results in detaching of the usb device + * fail totally, which results in detaching of the USB device * and immediate cleanup of the usbdev_t structure. * In the latter case the caller has to make sure, that he won't * use the device any more. @@ -703,14 +703,14 @@ usb_msc_poll (usbdev_t *dev) return; if (!prev_ready && msc->ready) { - usb_debug ("usb msc: not ready -> ready (lun %d)\n", msc->lun); + usb_debug ("USB msc: not ready -> ready (lun %d)\n", msc->lun); usb_msc_create_disk (dev); } else if (prev_ready && !msc->ready) { - usb_debug ("usb msc: ready -> not ready (lun %d)\n", msc->lun); + usb_debug ("USB msc: ready -> not ready (lun %d)\n", msc->lun); usb_msc_remove_disk (dev); } else if (!prev_ready && !msc->ready) { u8 new_lun = (msc->lun + 1) % msc->num_luns; - usb_debug("usb msc: not ready (lun %d) -> lun %d\n", msc->lun, + usb_debug("USB msc: not ready (lun %d) -> lun %d\n", msc->lun, new_lun); msc->lun = new_lun; } diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index 8505c4f60b..5d27f7cbc6 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -217,7 +217,7 @@ struct usbdev { hci_t *controller; endpoint_t endpoints[32]; int num_endp; - int address; // usb address + int address; // USB address int hub; // hub, device is attached to int port; // port where device is attached usb_speed speed; @@ -263,7 +263,7 @@ struct usbdev_hc { u8* (*poll_intr_queue) (void *queue); void *instance; - /* set_address(): Tell the usb device its address (xHCI + /* set_address(): Tell the USB device its address (xHCI controllers want to do this by themselves). Also, allocate the usbdev structure, initialize enpoint 0 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 5a3f2a6e89..97b39f46a0 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -382,7 +382,7 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) u32 portsc; int loop; - /* Reset the usb debug port */ + /* Reset the USB debug port */ portsc = read32(&ehci_regs->port_status[port - 1]); portsc &= ~PORT_PE; portsc |= PORT_RESET; diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 13819f1b90..35f75c4232 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -67,7 +67,7 @@ void mainboard_late_rcba_config(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, -1 }, /* P2: Camera (no OC) */ @@ -120,7 +120,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index c234e5b848..7d1c177d92 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -154,7 +154,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 0, 0, -1 }, /* P0: Empty */ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index e36a1c70a7..4a109f13d7 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -26,7 +26,7 @@ static struct usb_board_data usb1_board_data = { static void setup_usb(void) { - /* Setting Secondary usb controller */ + /* Setting Secondary USB controller */ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); } diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 421826cdeb..864837bbd4 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -145,7 +145,7 @@ static void configure_usb(void) static void configure_usb_hub(void) { - /* set usb hub reset pin (low active) to high */ + /* set USB hub reset pin (low active) to high */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) gpio_output(GPIO(UTXD3), 1); } diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 01c452637d..917d16591e 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -116,7 +116,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 0, 0, -1 }, /* P0: Empty */ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 07c19c5ae0..b4e96f0dd3 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -131,7 +131,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ { 0, 1, 0x0000 }, /* P2: Empty */ @@ -171,7 +171,7 @@ int mainboard_should_reset_usb(int s3resume) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ {0, 0, 0}, /* P2: Empty */ diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 2d97c8599c..0bc5884e6a 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -111,7 +111,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, 0 }, /* P0: Front port (OC0) */ { 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h index ce059fd8fd..c59cfd02f8 100644 --- a/src/mainboard/intel/harcuvar/hsio.h +++ b/src/mainboard/intel/harcuvar/hsio.h @@ -38,7 +38,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { * Lane[19]->USB3 rear I/O panel connector */ - /* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */ + /* SKU HSIO 20 (pcie [0-15] sata [16-18] USB [19]) */ {BL_SKU_HSIO_20, {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4}, {/* ME_FIA_MUX_CONFIG */ @@ -155,7 +155,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */ + /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] USB [19]) */ {BL_SKU_HSIO_12, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/*ME_FIA_MUX_CONFIG */ @@ -272,7 +272,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */ + /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] USB [19]) */ {BL_SKU_HSIO_10, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -388,7 +388,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */ + /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] USB [19]) */ {BL_SKU_HSIO_08, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -504,7 +504,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */ + /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] USB [19]) */ {BL_SKU_HSIO_06, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index eac19f47bb..df5f57e29a 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -99,7 +99,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ @@ -127,7 +127,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 04ddbe070f..7da2c55533 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -26,9 +26,9 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* SSP1: right */ { 1, 0, 1 }, /* SSP2: left, EHCI Debug */ - { 1, 1, 3 }, /* SSP3: dock usb3 */ - { 1, 1, -1 }, /* B0P4: wwan usb */ - { 1, 1, 2 }, /* B0P5: dock usb2 */ + { 1, 1, 3 }, /* SSP3: dock USB3 */ + { 1, 1, -1 }, /* B0P4: wwan USB */ + { 1, 1, 2 }, /* B0P5: dock USB2 */ { 0, 0, -1 }, /* B0P6 */ { 0, 0, -1 }, /* B0P7 */ { 1, 2, -1 }, /* B0P8: unknown */ @@ -36,7 +36,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 2, 5 }, /* B1P2 */ { 1, 1, -1 }, /* B1P3: fingerprint reader */ { 0, 0, -1 }, /* B1P4 */ - { 1, 1, -1 }, /* B1P5: wlan usb */ + { 1, 1, -1 }, /* B1P5: wlan USB */ { 1, 1, -1 }, /* B1P6: Camera */ }; diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 33802537ab..0249c3bc56 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -178,7 +178,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 1, 0 }, /* P0: Port 0 (OC0) */ { 1, 1, 1 }, /* P1: Port 1 (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index d7f9b907be..13da85ada6 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -167,7 +167,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 1, 0 }, /* P0: Front port (OC0) */ { 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h index e49fefd23f..aa6af53cbb 100644 --- a/src/mainboard/scaleway/tagada/hsio.h +++ b/src/mainboard/scaleway/tagada/hsio.h @@ -38,7 +38,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { * Lane[19]->USB3 rear I/O panel connector */ - /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_20, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -155,7 +155,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_12, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -273,7 +273,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_10, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -391,7 +391,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_08, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -509,7 +509,7 @@ const BL_HSIO_INFORMATION tagada_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */ + /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] USB []) */ {BL_SKU_HSIO_06, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b9c5a4fa27..03e6dbd038 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -842,7 +842,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) /* * Override GLK xhci clock gating register(XHCLKGTEN) to - * mitigate usb device suspend and resume failure. + * mitigate USB device suspend and resume failure. */ if (CONFIG(SOC_INTEL_GLK)) { uint32_t *cfg; diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index 0fd41bfdf0..d8ee29c9ff 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -84,7 +84,7 @@ static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event) /* * Check if CSC bit is set and port is capable of wake on * connect/disconnect to identify if the port caused wake - * event for usb attach/detach. + * event for USB attach/detach. */ if (pch_xhci_csc_set(port_status) && pch_xhci_wake_capable(port_status)) { @@ -95,7 +95,7 @@ static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event) /* * Check if PLC is set and PLS indicates resume to identify if - * the port caused wake event for usb activity. + * the port caused wake event for USB activity. */ if (pch_xhci_plc_set(port_status) && pch_xhci_resume(port_status)) { diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index d80cfe98b3..b148093af0 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -104,7 +104,7 @@ static int check_ip_clk_status(void) do { if (stopwatch_expired(&sw)) { - u3p_err("usb clocks are not stable!!!\n"); + u3p_err("USB clocks are not stable!!!\n"); return -1; } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index d6003bede2..21c578fa30 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -214,7 +214,7 @@ static struct device_operations usb_ops = { }; /* - * The pci id of usb ctrl 0 and 1 are the same. + * The pci id of USB ctrl 0 and 1 are the same. */ static const struct pci_driver usb_ohci123_driver __pci_driver = { .ops = &usb_ops, diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index a627cc15c7..fa578f7cec 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -99,7 +99,7 @@ void i82801gx_early_init(void) reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - /* usb transient disconnect */ + /* USB transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); diff --git a/util/uio_usbdebug/uio_usbdebug_intel.c b/util/uio_usbdebug/uio_usbdebug_intel.c index 9271896b7d..2295cabbc7 100644 --- a/util/uio_usbdebug/uio_usbdebug_intel.c +++ b/util/uio_usbdebug/uio_usbdebug_intel.c @@ -52,7 +52,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx) void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { - /* claim usb debug port */ + /* claim USB debug port */ const unsigned long dbgctl_addr = ((unsigned long)ehci_bar) + CONFIG_EHCI_DEBUG_OFFSET; write32(dbgctl_addr, read32(dbgctl_addr) | (1 << 30));