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soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representation 

For easier review of the switch to a new register struct in the
follow-up change, the panel delay times get converted from destination
register raw format to milliseconds representation in this change.

Formula for conversion of power cycle delay:

  gpu_panel_power_cycle_delay_ms =
    (gpu_panel_power_cycle_delay - 1) * 100

Formula for all others:

  gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10

The register names gain a suffix `_ms` and calculation of the
destination register raw values gets done in gma code now.

Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michael Niewöhner 2020-12-28 15:00:39 +01:00
parent 9e38efc27b
commit 44fa0d4ca0
17 changed files with 88 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/google/auron/variants/auron_paine/overridetree.cb
View File

@ -1,11 +1,11 @@
chip soc/intel/broadwell chip soc/intel/broadwell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay_ms" = "40"
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay_ms" = "15"
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_on_delay_ms" = "7"
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay_ms" = "210"
device domain 0 on device domain 0 on
chip soc/intel/broadwell/pch chip soc/intel/broadwell/pch

10
src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
View File

@ -1,11 +1,11 @@
chip soc/intel/broadwell chip soc/intel/broadwell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay_ms" = "40"
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay_ms" = "15"
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_on_delay_ms" = "210"
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay_ms" = "210"
device domain 0 on device domain 0 on
chip soc/intel/broadwell/pch chip soc/intel/broadwell/pch

10
src/mainboard/google/auron/variants/buddy/overridetree.cb
View File

@ -1,11 +1,11 @@
chip soc/intel/broadwell chip soc/intel/broadwell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay_ms" = "40"
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay_ms" = "15"
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_on_delay_ms" = "7"
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay_ms" = "210"
register "s0ix_enable" = "0" register "s0ix_enable" = "0"

10
src/mainboard/google/auron/variants/gandof/overridetree.cb
View File

@ -1,11 +1,11 @@
chip soc/intel/broadwell chip soc/intel/broadwell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay_ms" = "40"
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay_ms" = "15"
register "gpu_panel_power_backlight_on_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay_ms" = "50"
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay_ms" = "210"
device domain 0 on device domain 0 on
chip soc/intel/broadwell/pch chip soc/intel/broadwell/pch

10
src/mainboard/google/auron/variants/lulu/overridetree.cb
View File

@ -1,11 +1,11 @@
chip soc/intel/broadwell chip soc/intel/broadwell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay_ms" = "40"
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay_ms" = "15"
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_on_delay_ms" = "7"
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay_ms" = "210"
device domain 0 on device domain 0 on
chip soc/intel/broadwell/pch chip soc/intel/broadwell/pch

10
src/mainboard/google/auron/variants/samus/overridetree.cb
View File

@ -4,11 +4,11 @@ chip soc/intel/broadwell
register "gpu_dp_c_hotplug" = "0x06" register "gpu_dp_c_hotplug" = "0x06"
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_cycle_delay_ms" = "500"
register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_up_delay_ms" = "200"
register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_down_delay_ms" = "50"
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_on_delay_ms" = "200"
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay_ms" = "200"
register "vr_slow_ramp_rate_set" = "3" register "vr_slow_ramp_rate_set" = "3"
register "vr_slow_ramp_rate_enable" = "1" register "vr_slow_ramp_rate_enable" = "1"

10
src/mainboard/google/slippy/variants/falco/overridetree.cb
View File

@ -1,11 +1,11 @@
chip northbridge/intel/haswell chip northbridge/intel/haswell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) register "gpu_panel_power_up_delay_ms" = "60"
register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) register "gpu_panel_power_down_delay_ms" = "60"
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) register "gpu_panel_power_backlight_on_delay_ms" = "210"
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) register "gpu_panel_power_backlight_off_delay_ms" = "210"
device domain 0 on device domain 0 on

10
src/mainboard/google/slippy/variants/leon/overridetree.cb
View File

@ -1,11 +1,11 @@
chip northbridge/intel/haswell chip northbridge/intel/haswell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay_ms" = "40"
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay_ms" = "15"
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_on_delay_ms" = "210"
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay_ms" = "210"
device domain 0 on device domain 0 on

10
src/mainboard/google/slippy/variants/peppy/overridetree.cb
View File

@ -1,11 +1,11 @@
chip northbridge/intel/haswell chip northbridge/intel/haswell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay_ms" = "40"
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay_ms" = "15"
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_on_delay_ms" = "210"
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay_ms" = "210"
device domain 0 on device domain 0 on

10
src/mainboard/google/slippy/variants/wolf/overridetree.cb
View File

@ -1,11 +1,11 @@
chip northbridge/intel/haswell chip northbridge/intel/haswell
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) register "gpu_panel_power_cycle_delay_ms" = "500"
register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) register "gpu_panel_power_up_delay_ms" = "200"
register "gpu_panel_power_down_delay" = "500" # 50ms (T10) register "gpu_panel_power_down_delay_ms" = "50"
register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) register "gpu_panel_power_backlight_on_delay_ms" = "1"
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) register "gpu_panel_power_backlight_off_delay_ms" = "200"
device domain 0 on device domain 0 on

10
src/mainboard/hp/folio_9480m/devicetree.cb
View File

@ -4,11 +4,11 @@ chip northbridge/intel/haswell
register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gfx" = "GMA_STATIC_DISPLAYS(0)"
register "gpu_dp_b_hotplug" = "4" register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4" register "gpu_dp_c_hotplug" = "4"
register "gpu_panel_power_backlight_off_delay" = "1" register "gpu_panel_power_backlight_off_delay_ms" = "1"
register "gpu_panel_power_backlight_on_delay" = "1" register "gpu_panel_power_backlight_on_delay_ms" = "1"
register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_cycle_delay_ms" = "500"
register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_down_delay_ms" = "50"
register "gpu_panel_power_up_delay" = "2000" register "gpu_panel_power_up_delay_ms" = "200"
register "gpu_pch_backlight_pwm_hz" = "200" register "gpu_pch_backlight_pwm_hz" = "200"
register "usb_xhci_on_resume" = "true" register "usb_xhci_on_resume" = "true"
device cpu_cluster 0 on device cpu_cluster 0 on

10
src/mainboard/lenovo/t440p/devicetree.cb
View File

@ -4,11 +4,11 @@ chip northbridge/intel/haswell
register "gpu_dp_b_hotplug" = "4" register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4" register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4" register "gpu_dp_d_hotplug" = "4"
register "gpu_panel_power_backlight_off_delay" = "1" register "gpu_panel_power_backlight_off_delay_ms" = "1"
register "gpu_panel_power_backlight_on_delay" = "1" register "gpu_panel_power_backlight_on_delay_ms" = "1"
register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_cycle_delay_ms" = "500"
register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_down_delay_ms" = "50"
register "gpu_panel_power_up_delay" = "2000" register "gpu_panel_power_up_delay_ms" = "200"
register "gpu_pch_backlight_pwm_hz" = "220" register "gpu_pch_backlight_pwm_hz" = "220"
register "ec_present" = "true" register "ec_present" = "true"
device cpu_cluster 0x0 on device cpu_cluster 0x0 on

10
src/mainboard/purism/librem_bdw/devicetree.cb
View File

@ -10,11 +10,11 @@ chip soc/intel/broadwell
register "gpu_pch_backlight_pwm_hz" = "200" register "gpu_pch_backlight_pwm_hz" = "200"
# Set panel power delays # Set panel power delays
register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_cycle_delay_ms" = "500"
register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_up_delay_ms" = "200"
register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_down_delay_ms" = "50"
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_on_delay_ms" = "200"
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay_ms" = "200"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end

10
src/northbridge/intel/haswell/chip.h
View File

@ -17,11 +17,11 @@ struct northbridge_intel_haswell_config {
u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_cycle_delay_ms; /* T4 time sequence */
u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_up_delay_ms; /* T1+T2 time sequence */
u16 gpu_panel_power_down_delay; /* T3 time sequence */ u16 gpu_panel_power_down_delay_ms; /* T3 time sequence */
u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_on_delay_ms; /* T5 time sequence */
u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ u16 gpu_panel_power_backlight_off_delay_ms; /* Tx time sequence */
unsigned int gpu_pch_backlight_pwm_hz; unsigned int gpu_pch_backlight_pwm_hz;
enum { enum {

12
src/northbridge/intel/haswell/gma.c
View File

@ -257,24 +257,24 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power On Delays */ /* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS); reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) { if (!reg32) {
reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_ON_DELAYS, reg32); gtt_write(PCH_PP_ON_DELAYS, reg32);
} }
/* Setup Panel Power Off Delays */ /* Setup Panel Power Off Delays */
reg32 = gtt_read(PCH_PP_OFF_DELAYS); reg32 = gtt_read(PCH_PP_OFF_DELAYS);
if (!reg32) { if (!reg32) {
reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_OFF_DELAYS, reg32); gtt_write(PCH_PP_OFF_DELAYS, reg32);
} }
/* Setup Panel Power Cycle Delay */ /* Setup Panel Power Cycle Delay */
if (conf->gpu_panel_power_cycle_delay) { if (conf->gpu_panel_power_cycle_delay_ms) {
reg32 = gtt_read(PCH_PP_DIVISOR); reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0x1f; reg32 &= ~0x1f;
reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f;
gtt_write(PCH_PP_DIVISOR, reg32); gtt_write(PCH_PP_DIVISOR, reg32);
} }

10
src/soc/intel/broadwell/chip.h
View File

@ -19,11 +19,11 @@ struct soc_intel_broadwell_config {
u8 gpu_dp_d_hotplug; u8 gpu_dp_d_hotplug;
/* Panel power sequence timings */ /* Panel power sequence timings */
u8 gpu_panel_power_cycle_delay; u16 gpu_panel_power_cycle_delay_ms;
u16 gpu_panel_power_up_delay; u16 gpu_panel_power_up_delay_ms;
u16 gpu_panel_power_down_delay; u16 gpu_panel_power_down_delay_ms;
u16 gpu_panel_power_backlight_on_delay; u16 gpu_panel_power_backlight_on_delay_ms;
u16 gpu_panel_power_backlight_off_delay; u16 gpu_panel_power_backlight_off_delay_ms;
/* Panel backlight settings */ /* Panel backlight settings */
unsigned int gpu_pch_backlight_pwm_hz; unsigned int gpu_pch_backlight_pwm_hz;

13
src/soc/intel/broadwell/gma.c
View File

@ -4,6 +4,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <bootmode.h> #include <bootmode.h>
#include <commonlib/helpers.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
#include <device/device.h> #include <device/device.h>
@ -298,24 +299,24 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power On Delays */ /* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS); reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) { if (!reg32) {
reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_ON_DELAYS, reg32); gtt_write(PCH_PP_ON_DELAYS, reg32);
} }
/* Setup Panel Power Off Delays */ /* Setup Panel Power Off Delays */
reg32 = gtt_read(PCH_PP_OFF_DELAYS); reg32 = gtt_read(PCH_PP_OFF_DELAYS);
if (!reg32) { if (!reg32) {
reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_OFF_DELAYS, reg32); gtt_write(PCH_PP_OFF_DELAYS, reg32);
} }
/* Setup Panel Power Cycle Delay */ /* Setup Panel Power Cycle Delay */
if (conf->gpu_panel_power_cycle_delay) { if (conf->gpu_panel_power_cycle_delay_ms) {
reg32 = gtt_read(PCH_PP_DIVISOR); reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0x1f; reg32 &= ~0x1f;
reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f;
gtt_write(PCH_PP_DIVISOR, reg32); gtt_write(PCH_PP_DIVISOR, reg32);
} }