intel/minnow3: Clean up Kconfig, devicetree and FMAP
This patch cleans up the code by:
o adding necessary default definitions to Kconfig
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
devicetree.cb and minnow3.fmd carried over a lot of code from google/reef
which is not correct for Minnow3 hardware. Minnow3 is not intended to
boot Chrome OS and does not need Chrome related flash regions. The
erroneous code is removed.
These changes are the same as those done for leafhill in commit:
6a48923 mainboard/intel/leafhill: Clean up
This was tested by building with the new configuration and
booting to UEFI Payload
Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18963
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brenton Dong
Martin Roth
parent
9931f66581
commit
44ff10eaa6
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@ -14,4 +14,64 @@ config MAINBOARD_PART_NUMBER
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string
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default "Minnow3"
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config FMDFILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/minnow3.fmd"
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config UART_FOR_CONSOLE
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int "Number of UART port to use for serial log"
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default 2
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config NEED_IFWI
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# this must be set to y
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bool "Use IFWI stitching"
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default n
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config IFWI_FMAP_NAME
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string "section in .fmd file to place ifwi blob"
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depends on NEED_IFWI
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default "IFWI"
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config IFWI_FILE_NAME
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string "path to image coming from FIT tool"
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depends on NEED_IFWI
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default ""
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config IFD_BIN_PATH
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string "path to descriptor.bin"
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depends on NEED_IFWI
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default ""
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config HAVE_IFD_BIN
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bool
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depends on NEED_IFWI
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default y
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config SOC_UART_DEBUG
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bool "use serial port debugging"
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default y
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config ADD_FSP_BINARIES
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bool "Add FSP blobs"
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depends on PLATFORM_USES_FSP2_0
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default n
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config FSP_M_FILE
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string "path to FSP-M.Fv blob"
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depends on ADD_FSP_BINARIES
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default ""
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config FSP_S_FILE
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string "path to FSP-S.Fv blob"
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depends on ADD_FSP_BINARIES
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default ""
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config FSP_S_CBFS
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string
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default "fsps.bin"
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config FSP_M_CBFS
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string
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default "fspm.bin"
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endif # BOARD_INTEL_MINNOW3
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@ -1,227 +1,56 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
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# GPIO for PERST_0
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# If the Board has PERST_0 signal, assign the GPIO
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# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
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register "prt0_gpio" = "GPIO_122"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [14:8] steps of delay for HS400, each 125ps.
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# [6:0] steps of delay for SDR104/HS200, each 125ps.
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register "emmc_tx_data_cntl1" = "0x0C16"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_tx_data_cntl2" = "0x28162828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_rx_cmd_data_cntl1" = "0x00181717"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [17:16] stands for Rx Clock before Output Buffer
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
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# [6:0] steps of delay for HS200, each 125ps.
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register "emmc_rx_cmd_data_cntl2" = "0x10008"
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# Enable DPTF
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register "dptf_enable" = "1"
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# PL1 override 12000 mW: the energy calculation is wrong with the
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# current VR solution. Experiments show that SoC TDP max (6W) can
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# be reached when RAPL PL1 is set to 12W.
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register "tdp_pl1_override_mw" = "12000"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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register "hdaudio_pwr_gate_enable" = "1"
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register "hdaudio_bios_config_lockdown" = "1"
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# Enable lpss s0ix
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register "lpss_s0ix_enable" = "1"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route, i.e., if this route changes then the affected GPE
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# offset bits also need to be changed. This sets the PMC register
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# GPE_CFG fields.
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register "gpe0_dw1" = "PMC_GPE_N_31_0"
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register "gpe0_dw2" = "PMC_GPE_N_63_32"
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register "gpe0_dw3" = "PMC_GPE_SW_31_0"
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# Enable I2C0 for audio codec at 400kHz
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register "i2c[0]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 104,
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.fall_time_ns = 52,
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}"
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# Enable I2C2 bus early for TPM at 400kHz
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register "i2c[2]" = "{
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 57,
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.fall_time_ns = 28,
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}"
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# touchscreen at 400kHz
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register "i2c[3]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 76,
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.fall_time_ns = 164,
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}"
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# trackpad at 400kHz
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register "i2c[4]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 114,
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.fall_time_ns = 164,
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}"
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# digitizer at 400kHz
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register "i2c[5]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 152,
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.fall_time_ns = 30,
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}"
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# Minimum SLP S3 assertion width 28ms.
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register "slp_s3_assertion_width_usecs" = "28000"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on # - Audio
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chip drivers/generic/max98357a
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
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register "sdmode_delay" = "5"
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device generic 0 on end
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end
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end
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device pci 11.0 off end # - ISH
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device pci 12.0 off end # - SATA
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device pci 13.0 off end # - Root Port 2 - PCIe-A 0
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device pci 13.1 off end # - Root Port 3 - PCIe-A 1
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device pci 13.2 off end # - Root Port 4 - PCIe-A 2
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device pci 13.3 off end # - Root Port 5 - PCIe-A 3
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device pci 14.0 on
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chip drivers/intel/wifi
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register "wake" = "GPE0_DW3_00"
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device pci 00.0 on end
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end
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end # - Root Port 0 - PCIe-B 0 - Wifi
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device pci 14.1 off end # - Root Port 1 - PCIe-B 1
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device pci 15.0 on end # - XHCI
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device pci 15.1 off end # - XDCI
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device pci 16.0 on # - I2C 0
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chip drivers/i2c/da7219
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
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register "btn_cfg" = "50"
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register "mic_det_thr" = "500"
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register "jack_ins_deb" = "20"
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register "jack_det_rate" = ""32ms_64ms""
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register "jack_rem_deb" = "1"
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register "a_d_btn_thr" = "0xa"
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register "d_b_btn_thr" = "0x16"
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register "b_c_btn_thr" = "0x21"
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register "c_mic_btn_thr" = "0x3e"
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register "btn_avg" = "4"
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register "adc_1bit_rpt" = "1"
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register "micbias_lvl" = "2600"
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register "mic_amp_in_sel" = ""diff""
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device i2c 1a on end
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end
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end
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
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device i2c 50 on end
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end
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end # - I2C 2
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device pci 16.3 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
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register "reset_delay_ms" = "20"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
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register "enable_delay_ms" = "1"
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register "has_power_resource" = "1"
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device i2c 10 on end
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end
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end # - I2C 3
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device pci 17.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)"
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register "wake" = "GPE0_DW1_15"
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register "probed" = "1"
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device i2c 15 on end
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end
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end # - I2C 4
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device pci 17.1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""WCOM50C1""
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register "generic.desc" = ""WCOM Digitizer""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
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register "hid_desc_reg_offset" = "0x1"
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device i2c 0x9 on end
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end
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end # - I2C 5
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device pci 17.2 off end # - I2C 6
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device pci 17.3 off end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 off end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 off end # - SPI 1
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device pci 19.2 off end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 on end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 off end # - SDIO
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device pci 1f.0 on # - LPC
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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device pci 1f.1 on end # - SMBUS
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on end # - Audio
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device pci 11.0 on end # - ISH
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device pci 12.0 on end # - SATA
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device pci 13.0 on end # - PCIe-A 0
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device pci 13.2 on end # - Onboard Lan
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device pci 13.3 on end # - PCIe-A 3
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device pci 14.0 on end # - PCIe-B 0
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device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT)
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device pci 15.0 on end # - XHCI
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device pci 15.1 on end # - XDCI
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device pci 16.0 on end # - I2C 0
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on end # - I2C 2
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device pci 16.3 on end # - I2C 3
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device pci 17.0 on end # - I2C 4
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device pci 17.1 on end # - I2C 5
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device pci 17.2 on end # - I2C 6
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device pci 17.3 on end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 on end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 on end # - SPI 1
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device pci 19.2 on end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 on end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 on end # - SDIO
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device pci 1f.0 on end # - LPC
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device pci 1f.1 on end # - SMBUS
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end
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end
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@ -1,40 +1,13 @@
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FLASH 16M {
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WP_RO@0x0 0x480000 {
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SI_DESC@0x0 0x1000
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IFWI@0x1000 0x27f000
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RO_VPD@0x280000 0x4000
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RO_SECTION@0x284000 0x1fc000 {
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FMAP@0x0 0x800
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COREBOOT(CBFS)@0x1000 0x1bb000
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RO_UNUSED@0x1bc000 0x40000
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}
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SI_DESC@0x0 0x1000
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IFWI@0x1000 0x300000
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FMAP@0x301000 0x800
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COREBOOT(CBFS)@0x301800 0x3dc800
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UNIFIED_MRC_CACHE@0x6de000 0x21000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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RW_VAR_MRC_CACHE@0x20000 0x1000
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}
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MISC_RW@0x480000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x21000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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RW_VAR_MRC_CACHE@0x20000 0x1000
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}
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RW_ELOG@0x21000 0x3000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x28000 0x2000
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RW_NVRAM@0x2a000 0x6000
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}
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RW_LEGACY(CBFS)@0xd30000 0x200000
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BIOS_UNUSABLE@0xf30000 0x4f000
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DEVICE_EXTENSION@0xf7f000 0x80000
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# Currently, it is required that the BIOS region be a multiple of 8KiB.
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# This is required so that the recovery mechanism can find SIGN_CSE
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# region aligned to 4K at the center of BIOS region. Since the
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# descriptor at the beginning uses 4K and BIOS starts at an offset of
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# 4K, a hole of 4K is created towards the end of the flash to compensate
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# for the size requirement of BIOS region.
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# FIT tool thus creates descriptor with following regions:
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# Descriptor --> 0 to 4K
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# BIOS --> 4K to 0xf7f000
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# Device ext --> 0xf7f000 to 0xfff000
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UNUSED_HOLE@0xfff000 0x1000
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DEVICE_EXTENSION@0x6ff000 0x100000
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UNUSED_HOLE@0x7ff000 0x1000
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}
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