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nb/intel/ironlake: Correct PCIEXBAR definition 

This register resides within the SAD's config space, and is 64-bit.

Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-07-22 16:43:48 +02:00 committed by Patrick Georgi
parent 3ab19b32a2
commit 4500893062
4 changed files with 5 additions and 4 deletions
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2
src/northbridge/intel/ironlake/acpi.c
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@ -13,7 +13,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
u32 pciexbar_reg;
int max_buses;
pciexbar_reg = pci_read_config32(QPI_SAD, 0x50);
pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))

4
src/northbridge/intel/ironlake/bootblock.c
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@ -6,6 +6,6 @@
void bootblock_early_northbridge_init(void)
{
pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1);
pci_io_write_config32(QPI_SAD, 0x54, 0);
pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0);
}

1
src/northbridge/intel/ironlake/hostbridge_regs.h
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@ -11,7 +11,6 @@
#define DEVEN_PEG10 (1 << 1)
#define DEVEN_HOST (1 << 0)
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define LAC 0x87 /* Legacy Access Control */

2
src/northbridge/intel/ironlake/ironlake.h
View File

@ -55,6 +55,8 @@
#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */
#define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
#define SAD_PCIEXBAR 0x50
/* Device 0:2.0 PCI configuration space (Graphics Device) */