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AMD amdfam10: Drop EXT_CONF_SUPPORT 

Only used for AMD K8 siemens/sitemp_g1p1 with southbridge rs690.

Change-Id: Ie98a77ce190b1bd35996c7f25da0a0fe9819c9c3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7809
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki 2014-12-14 08:35:29 +02:00
parent ac7402dc11
commit 450335918c
8 changed files with 70 additions and 409 deletions
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4
src/cpu/amd/socket_AM2r2/Kconfig
View File

@ -15,10 +15,6 @@ config EXT_RT_TBL_SUPPORT
bool bool
default n default n
config EXT_CONF_SUPPORT
bool
default n
config CBB config CBB
hex hex
default 0x0 default 0x0

4
src/cpu/amd/socket_AM3/Kconfig
View File

@ -15,10 +15,6 @@ config EXT_RT_TBL_SUPPORT
bool bool
default n default n
config EXT_CONF_SUPPORT
bool
default n
config CBB config CBB
hex hex
default 0x0 default 0x0

4
src/cpu/amd/socket_ASB2/Kconfig
View File

@ -15,10 +15,6 @@ config EXT_RT_TBL_SUPPORT
bool bool
default n default n
config EXT_CONF_SUPPORT
bool
default n
config CBB config CBB
hex hex
default 0x0 default 0x0

4
src/cpu/amd/socket_C32/Kconfig
View File

@ -15,10 +15,6 @@ config EXT_RT_TBL_SUPPORT
bool bool
default n default n
config EXT_CONF_SUPPORT
bool
default n
config CBB config CBB
hex hex
default 0x0 default 0x0

4
src/cpu/amd/socket_F_1207/Kconfig
View File

@ -14,10 +14,6 @@ config EXT_RT_TBL_SUPPORT
bool bool
default n default n
config EXT_CONF_SUPPORT
bool
default n
config CBB config CBB
hex hex
default 0x0 default 0x0

270
src/northbridge/amd/amdfam10/conf.c
View File

@ -38,13 +38,6 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
dev = __f1_dev[0]; dev = __f1_dev[0];
#endif #endif
#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
pci_write_config32(dev, 0x110, nodeid | (0<<28));
d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8];
#else
u32 temp; u32 temp;
temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
@ -57,7 +50,6 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.base |= temp<<21; d.base |= temp<<21;
#endif
return d; return d;
} }
@ -66,15 +58,6 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
{ {
u32 i; u32 i;
device_t dev; device_t dev;
#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
u32 d_base_i, d_base_d, d_mask_i, d_mask_d;
d_base_i = nodeid | (0<<28);
d_base_d = d.base | nodeid; //[47:27] at [28:8];
d_mask_i = nodeid | (1<<28); // [47:27] at [28:8]
d_mask_d = d.mask; // enable is bit 0
#else
u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi; u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi;
u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg; u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg;
d_mask_lo = (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones d_mask_lo = (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones
@ -86,7 +69,6 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
d_mask_hi_reg = 0x144+(nodeid<<3); d_mask_hi_reg = 0x144+(nodeid<<3);
d_base_lo_reg = 0x40+(nodeid<<3); d_base_lo_reg = 0x40+(nodeid<<3);
d_base_hi_reg = 0x140+(nodeid<<3); d_base_hi_reg = 0x140+(nodeid<<3);
#endif
for (i=0;i<nodes;i++) { for (i=0;i<nodes;i++) {
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)
@ -94,19 +76,10 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
#else #else
dev = __f1_dev[i]; dev = __f1_dev[i];
#endif #endif
#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
pci_write_config32(dev, 0x110, d_base_i);
pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8];
pci_write_config32(dev, 0x110, d_mask_i); // [47:27] at [28:8]
pci_write_config32(dev, 0x114, d_mask_d); // enable is bit 0
#else
pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones
pci_write_config32(dev, d_mask_hi_reg, d_mask_hi); pci_write_config32(dev, d_mask_hi_reg, d_mask_hi);
pci_write_config32(dev, d_base_lo_reg, d_base_lo); pci_write_config32(dev, d_base_lo_reg, d_base_lo);
pci_write_config32(dev, d_base_hi_reg, d_base_hi); pci_write_config32(dev, d_base_hi_reg, d_base_hi);
#endif
} }
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)
@ -321,67 +294,6 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
#endif // CONFIG_AMDMCT #endif // CONFIG_AMDMCT
#if CONFIG_EXT_CONF_SUPPORT
static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
u32 busn_min, u32 busn_max,
u32 type)
{
device_t dev;
u32 i;
u32 tempreg;
u32 index_min, index_max;
u32 dest_min, dest_max;
index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
#if defined(__PRE_RAM__)
dev = NODE_PCI(nodeid, 1);
#else
dev = __f1_dev[nodeid];
#endif
if (index_min== index_max) {
pci_write_config32(dev, 0x110, index_min | (type<<28));
tempreg = pci_read_config32(dev, 0x114);
for (i=dest_min; i<=dest_max; i++) {
tempreg &= ~(0xff<<(i*8));
tempreg |= (cfg_map_dest<<(i*8));
}
pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
pci_write_config32(dev, 0x114, tempreg);
} else if (index_min<index_max) {
pci_write_config32(dev, 0x110, index_min | (type<<28));
tempreg = pci_read_config32(dev, 0x114);
for (i=dest_min; i<=3; i++) {
tempreg &= ~(0xff<<(i*8));
tempreg |= (cfg_map_dest<<(i*8));
}
pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
pci_write_config32(dev, 0x114, tempreg);
pci_write_config32(dev, 0x110, index_max | (type<<28));
tempreg = pci_read_config32(dev, 0x114);
for (i=0; i<=dest_max; i++) {
tempreg &= ~(0xff<<(i*8));
tempreg |= (cfg_map_dest<<(i*8));
}
pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
pci_write_config32(dev, 0x114, tempreg);
if ((index_max-index_min)>1) {
tempreg = 0;
for (i=0; i<=3; i++) {
tempreg &= ~(0xff<<(i*8));
tempreg |= (cfg_map_dest<<(i*8));
}
for (i=index_min+1; i<index_max;i++) {
pci_write_config32(dev, 0x110, i | (type<<28));
pci_write_config32(dev, 0x114, tempreg);
}
}
}
}
#endif
static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 busn_min, u32 busn_max, u32 segbit, u32 busn_min, u32 busn_max, u32 segbit,
u32 nodes) u32 nodes)
@ -393,9 +305,6 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
busn_min>>=segbit; busn_min>>=segbit;
busn_max>>=segbit; busn_max>>=segbit;
#if CONFIG_EXT_CONF_SUPPORT
if (ht_c_index < 4) {
#endif
tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
for (i=0; i<nodes; i++) { for (i=0; i<nodes; i++) {
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)
@ -405,27 +314,6 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
#endif #endif
pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
} }
#if CONFIG_EXT_CONF_SUPPORT
return;
}
// if ht_c_index > 3, We should use extend space x114_x6
u32 cfg_map_dest;
u32 j;
// for nodeid at first
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, busn_min, busn_max, 6);
// all other nodes
cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
for (j = 0; j< nodes; j++) {
if (j== nodeid) continue;
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
}
#endif
} }
static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
@ -434,9 +322,6 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 i; u32 i;
device_t dev; device_t dev;
#if CONFIG_EXT_CONF_SUPPORT
if (ht_c_index<4) {
#endif
for (i=0; i<nodes; i++) { for (i=0; i<nodes; i++) {
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1); dev = NODE_PCI(i, 1);
@ -445,22 +330,6 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
#endif #endif
pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
} }
#if CONFIG_EXT_CONF_SUPPORT
return;
}
// if hc_c_index >3, We should use busn_min and busn_max to clear extend space
u32 cfg_map_dest;
u32 j;
// all nodes
cfg_map_dest = 0;
for (j = 0; j< nodes; j++) {
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
}
#endif
} }
#if CONFIG_PCI_BUS_SEGN_BITS #if CONFIG_PCI_BUS_SEGN_BITS
@ -493,9 +362,6 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 tempreg; u32 tempreg;
device_t dev; device_t dev;
#if CONFIG_EXT_CONF_SUPPORT
if (ht_c_index<4) {
#endif
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
for (i=0; i<nodes; i++) { for (i=0; i<nodes; i++) {
@ -515,29 +381,6 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
#endif #endif
pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
} }
#if CONFIG_EXT_CONF_SUPPORT
return;
}
u32 cfg_map_dest;
u32 j;
// if ht_c_index > 3, We should use extend space
if (io_min>io_max) return;
// for nodeid at first
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
// all other nodes
cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
for (j = 0; j< nodes; j++) {
if (j== nodeid) continue;
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
}
#endif
} }
@ -546,9 +389,6 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
{ {
u32 i; u32 i;
device_t dev; device_t dev;
#if CONFIG_EXT_CONF_SUPPORT
if (ht_c_index<4) {
#endif
/* io range allocation */ /* io range allocation */
for (i=0; i<nodes; i++) { for (i=0; i<nodes; i++) {
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)
@ -559,20 +399,6 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
} }
#if CONFIG_EXT_CONF_SUPPORT
return;
}
// : if hc_c_index > 3, We should use io_min, io_max to clear extend space
u32 cfg_map_dest;
u32 j;
// all nodes
cfg_map_dest = 0;
for (j = 0; j< nodes; j++) {
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
}
#endif
} }
#endif #endif
@ -597,13 +423,6 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
} }
} }
#if CONFIG_EXT_CONF_SUPPORT
u32 j;
// clear the extend space
for (j = 0; j< nodes; j++) {
set_addr_map_reg_4_6_in_one_node(j,0, 0, 0xff, 6);
}
#endif
for (ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) { for (ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) {
u32 nodeid, linkn; u32 nodeid, linkn;
@ -717,16 +536,9 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
u32 io_min, u32 io_max) u32 io_min, u32 io_max)
{ {
u32 val; u32 val;
#if CONFIG_EXT_CONF_SUPPORT
if (reg!=0x110) {
#endif
/* io range allocation */ /* io range allocation */
index = (reg-0xc0)>>3; index = (reg-0xc0)>>3;
#if CONFIG_EXT_CONF_SUPPORT
} else {
index+=4;
}
#endif
val = (nodeid & 0x3f); // 6 bits used val = (nodeid & 0x3f); // 6 bits used
sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid
@ -742,16 +554,9 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
u32 mmio_min, u32 mmio_max) u32 mmio_min, u32 mmio_max)
{ {
u32 val; u32 val;
#if CONFIG_EXT_CONF_SUPPORT
if (reg!=0x110) {
#endif
/* io range allocation */ /* io range allocation */
index = (reg-0x80)>>3; index = (reg-0x80)>>3;
#if CONFIG_EXT_CONF_SUPPORT
} else {
index+=8;
}
#endif
val = (nodeid & 0x3f) ; // 6 bits used val = (nodeid & 0x3f) ; // 6 bits used
sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn
@ -768,9 +573,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
{ {
u32 i; u32 i;
u32 tempreg; u32 tempreg;
#if CONFIG_EXT_CONF_SUPPORT
if (reg!=0x110) {
#endif
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
for (i=0; i<sysconf.nodes; i++) for (i=0; i<sysconf.nodes; i++)
@ -790,35 +593,13 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
#endif #endif
for (i=0; i<sysconf.nodes; i++) for (i=0; i<sysconf.nodes; i++)
pci_write_config32(__f1_dev[i], reg, tempreg); pci_write_config32(__f1_dev[i], reg, tempreg);
#if CONFIG_EXT_CONF_SUPPORT
return;
}
u32 cfg_map_dest;
u32 j;
// if ht_c_index > 3, We should use extend space
if (io_min>io_max) return;
// for nodeid at first
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
// all other nodes
cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
for (j = 0; j< sysconf.nodes; j++) {
if (j== nodeid) continue;
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
}
#endif
} }
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
{ {
u32 i; u32 i;
u32 tempreg; u32 tempreg;
#if CONFIG_EXT_CONF_SUPPORT
if (reg!=0x110) {
#endif
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
for (i=0; i<nodes; i++) for (i=0; i<nodes; i++)
@ -826,49 +607,6 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
for (i=0; i<sysconf.nodes; i++) for (i=0; i<sysconf.nodes; i++)
pci_write_config32(__f1_dev[i], reg, tempreg); pci_write_config32(__f1_dev[i], reg, tempreg);
#if CONFIG_EXT_CONF_SUPPORT
return;
}
device_t dev;
u32 j;
// if ht_c_index > 3, We should use extend space
// for nodeid at first
u32 enable;
if (mmio_min>mmio_max) {
return;
}
enable = 1;
dev = __f1_dev[nodeid];
tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
pci_write_config32(dev, 0x110, index | (2<<28));
pci_write_config32(dev, 0x114, tempreg);
tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
pci_write_config32(dev, 0x110, index | (3<<28));
pci_write_config32(dev, 0x114, tempreg);
// all other nodes
tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0);
for (j = 0; j< sysconf.nodes; j++) {
if (j== nodeid) continue;
dev = __f1_dev[j];
pci_write_config32(dev, 0x110, index | (2<<28));
pci_write_config32(dev, 0x114, tempreg);
}
tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
for (j = 0; j< sysconf.nodes; j++) {
if (j==nodeid) continue;
dev = __f1_dev[j];
pci_write_config32(dev, 0x110, index | (3<<28));
pci_write_config32(dev, 0x114, tempreg);
}
#endif
} }
#endif #endif

32
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -191,9 +191,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l
*/ */
ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf); ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf);
#if !CONFIG_EXT_CONF_SUPPORT
if(ht_c_index>=4) return max; if(ht_c_index>=4) return max;
#endif
/* Set up the primary, secondary and subordinate bus numbers. /* Set up the primary, secondary and subordinate bus numbers.
* We have no idea how many busses are behind this bridge yet, * We have no idea how many busses are behind this bridge yet,
@ -433,12 +431,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam10_find_iopair(dev, nodeid, link); resource = amdfam10_find_iopair(dev, nodeid, link);
if (resource) { if (resource) {
u32 align; u32 align;
#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
}
else
#endif
align = log2(HT_IO_HOST_ALIGN); align = log2(HT_IO_HOST_ALIGN);
resource->base = 0; resource->base = 0;
resource->size = 0; resource->size = 0;
@ -458,13 +450,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->limit = 0xffffffffffULL; resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE; resource->flags |= IORESOURCE_BRIDGE;
#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
#endif
} }
/* Initialize the memory constraints on the current bus */ /* Initialize the memory constraints on the current bus */
@ -476,11 +461,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN); resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL; resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
#endif
} }
} }
@ -1100,18 +1080,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
for(reg = 0xe0; reg <= 0xec; reg += 4) { for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0); f1_write_config32(reg, 0);
} }
#if CONFIG_EXT_CONF_SUPPORT
// all nodes
for(i = 0; i< sysconf.nodes; i++) {
int index;
for(index = 0; index < 64; index++) {
pci_write_config32(__f1_dev[i], 0x110, index | (6<<28));
pci_write_config32(__f1_dev[i], 0x114, 0);
}
}
#endif
for(link = dev->link_list; link; link = link->next) { for(link = dev->link_list; link; link = link->next) {
max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max);

25
src/northbridge/amd/amdfam10/reset_test.c
View File

@ -127,31 +127,6 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
} }
} }
#if CONFIG_EXT_CONF_SUPPORT
// let's check that in extend space
// use the nodeid extend space to find out the bus for the linkn
u32 tempreg;
int i;
int j;
u32 cfg_map_dest;
pci_devfn_t dev;
cfg_map_dest = (1<<7)|(1<<6)|link;
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
dev = NODE_PCI(node, 1);
for(j=0; j<64; j++) {
pci_io_write_config32(dev, 0x110, j | (6<<28));
tempreg = pci_io_read_config32(dev, 0x114);
for(i=0; i<=3; i++) {
tempreg >>= (i*8);
if((tempreg & ((1<<7)|(1<<6)|0x3f)) == cfg_map_dest) {
return (i+(j<<2)); //busn_min
}
}
}
#endif
return 0; return 0;
} }