Add (hacked-up) s3c24x0_i2c files
These are needed for communicating with the PMIC on Snow. We'll tidy them up as we go along... Change-Id: I197f59927eae0ad66191862d052de2a8873fb22f Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2078 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
David Hendricks
Ronald G. Minnich
parent
d3c7530908
commit
45256b3bfc
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@ -2,6 +2,7 @@ romstage-y += cpu_info.c
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romstage-y += pwm.c # needed by timer.c
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romstage-y += s5p_gpio.c
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romstage-y += timer.c
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romstage-y += s3c24x0_i2c.c
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#romstage-y += sromc.c
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#romstage-y += wdt.c
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@ -10,3 +11,4 @@ ramstage-y += cpu_info.c
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ramstage-y += pwm.c # needed by timer.c
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ramstage-y += timer.c
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ramstage-y += s5p_gpio.c
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ramstage-y += s3c24x0_i2c.c
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@ -0,0 +1,640 @@
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/*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same I2C controller inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#include <arch/io.h>
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#include "clk.h"
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#include "cpu/samsung/exynos5-common/clk.h"
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#include "cpu/samsung/exynos5250/cpu.h"
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#include "gpio.h"
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#include "cpu/samsung/exynos5250/gpio.h"
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#include "cpu/samsung/exynos5250/pinmux.h"
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//#include <fdtdec.h>
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#include "device/i2c.h"
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#include "s3c24x0_i2c.h"
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/* for board_i2c_* */
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#include "cpu/samsung/exynos5-common/spl.h"
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define I2C_OK 0
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#define I2C_NOK 1
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#define I2C_NACK 2
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#define I2C_NOK_LA 3 /* Lost arbitration */
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#define I2C_NOK_TOUT 4 /* time out */
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#define I2CSTAT_BSY 0x20 /* Busy bit */
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#define I2CSTAT_NACK 0x01 /* Nack bit */
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#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
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#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
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#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
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#define I2C_MODE_MR 0x80 /* Master Receive Mode */
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#define I2C_START_STOP 0x20 /* START / STOP */
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#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
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/* The timeouts we live by */
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enum {
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I2C_XFER_TIMEOUT_MS = 35, /* xfer to complete */
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I2C_INIT_TIMEOUT_MS = 1000, /* bus free on init */
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I2C_IDLE_TIMEOUT_MS = 100, /* waiting for bus idle */
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I2C_STOP_TIMEOUT_US = 200, /* waiting for stop events */
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};
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/* We should not rely on any particular ordering of these IDs */
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#if 0
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#ifndef CONFIG_OF_CONTROL
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static enum periph_id periph_for_dev[EXYNOS_I2C_MAX_CONTROLLERS] = {
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PERIPH_ID_I2C0,
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PERIPH_ID_I2C1,
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PERIPH_ID_I2C2,
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PERIPH_ID_I2C3,
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PERIPH_ID_I2C4,
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PERIPH_ID_I2C5,
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PERIPH_ID_I2C6,
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PERIPH_ID_I2C7,
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};
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#endif
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#endif
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static unsigned int g_current_bus __attribute__((section(".data")));
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static struct s3c24x0_i2c *g_early_i2c_config __attribute__((section(".data")));
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static struct s3c24x0_i2c_bus i2c_bus[EXYNOS_I2C_MAX_CONTROLLERS]
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__attribute__((section(".data")));
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static int i2c_busses __attribute__((section(".data")));
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void i2c_set_early_reg(unsigned int base)
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{
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g_early_i2c_config = (struct s3c24x0_i2c *)base;
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}
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static struct s3c24x0_i2c_bus *get_bus(int bus_idx)
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{
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/* If an early i2c config exists we just use that */
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if (g_early_i2c_config) {
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/* FIXME: value not retained from i2c_set_early_reg()? (but then, how
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* did if (!i2c) check pass earlier on? Corrupt value? */
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i2c_bus[0].regs = g_early_i2c_config;
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return &i2c_bus[0];
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}
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if (bus_idx < i2c_busses)
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return &i2c_bus[bus_idx];
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debug("Undefined bus: %d\n", bus_idx);
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return NULL;
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}
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static inline struct exynos5_gpio_part1 *exynos_get_base_gpio1(void)
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{
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return (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE);
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}
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static int WaitForXfer(struct s3c24x0_i2c *i2c)
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{
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int i;
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i = I2C_XFER_TIMEOUT_MS * 20;
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while (!(readl(&i2c->iiccon) & I2CCON_IRPND)) {
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if (i == 0) {
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debug("%s: i2c xfer timeout\n", __func__);
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return I2C_NOK_TOUT;
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}
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udelay(50);
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i--;
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}
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return I2C_OK;
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}
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static int IsACK(struct s3c24x0_i2c *i2c)
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{
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return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
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}
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static void ReadWriteByte(struct s3c24x0_i2c *i2c)
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{
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uint32_t x;
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x = readl(&i2c->iiccon);
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writel(x & ~I2CCON_IRPND, &i2c->iiccon);
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/* FIXME(dhendrix): cannot use nested macro (compilation failure) */
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// writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
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}
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static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
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{
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ulong freq, pres = 16, div;
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freq = clock_get_periph_rate(PERIPH_ID_I2C0);
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/* calculate prescaler and divisor values */
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if ((freq / pres / (16 + 1)) > speed)
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/* set prescaler to 512 */
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pres = 512;
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div = 0;
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while ((freq / pres / (div + 1)) > speed)
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div++;
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/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
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writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
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/* init to SLAVE REVEIVE and set slaveaddr */
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writel(0, &i2c->iicstat);
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writel(slaveadd, &i2c->iicadd);
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/* program Master Transmit (and implicit STOP) */
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writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
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}
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/* TODO: determine if this is necessary to init board using FDT-provided info */
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#if 0
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void board_i2c_init(const void *blob)
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{
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/*
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* Turn off the early i2c configuration and init the i2c properly,
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* this is done here to enable the use of i2c configs from FDT.
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*/
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i2c_set_early_reg(0);
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#ifdef CONFIG_OF_CONTROL
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int node_list[EXYNOS_I2C_MAX_CONTROLLERS];
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int i, count;
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count = fdtdec_find_aliases_for_id(blob, "i2c",
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COMPAT_SAMSUNG_S3C2440_I2C, node_list,
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EXYNOS_I2C_MAX_CONTROLLERS);
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for (i = 0; i < count; i++) {
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struct s3c24x0_i2c_bus *bus;
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int node = node_list[i];
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if (node < 0)
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continue;
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bus = &i2c_bus[i2c_busses];
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bus->regs = (struct s3c24x0_i2c *)
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fdtdec_get_addr(blob, node, "reg");
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bus->id = (enum periph_id)
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fdtdec_get_int(blob, node, "samsung,periph-id", -1);
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bus->node = node;
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bus->bus_num = i2c_busses++;
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}
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#else
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int i;
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for (i = 0; i < EXYNOS_I2C_MAX_CONTROLLERS; i++) {
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uintptr_t reg_addr = samsung_get_base_i2c() +
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EXYNOS_I2C_SPACING * i;
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i2c_bus[i].regs = (struct s3c24x0_i2c_bus *)reg_addr;
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i2c_bus[i].id = periph_for_dev[i];
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}
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i2c_busses = EXYNOS_I2C_MAX_CONTROLLERS;
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#endif
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}
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#endif
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/*
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* MULTI BUS I2C support
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*/
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/*
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* FIXME(dhendrix): not sure why this had to be guarded, but the code
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* should probably go into an exynos5-specific .c file if it really is
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* not generic.
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*/
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//#ifdef CONFIG_EXYNOS5
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static void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus)
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{
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exynos_pinmux_config(i2c->id, 0);
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i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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}
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//#else
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//#error "should not be here"
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//static void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus) {}
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//#endif
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#ifdef CONFIG_I2C_MULTI_BUS
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int i2c_set_bus_num(unsigned int bus)
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{
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struct s3c24x0_i2c_bus *i2c;
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i2c = get_bus(bus);
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if (!i2c)
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return -1;
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g_current_bus = bus;
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i2c_bus_init(i2c, g_current_bus);
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return 0;
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}
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unsigned int i2c_get_bus_num(void)
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{
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return g_current_bus;
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}
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#endif
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#ifdef CONFIG_OF_CONTROL
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int i2c_get_bus_num_fdt(const void *blob, int node)
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{
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enum fdt_compat_id compat;
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fdt_addr_t reg;
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int i;
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compat = fdtdec_lookup(blob, node);
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if (compat != COMPAT_SAMSUNG_S3C2440_I2C) {
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debug("%s: Not a supported I2C node\n", __func__);
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return -1;
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}
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reg = fdtdec_get_addr(blob, node, "reg");
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for (i = 0; i < i2c_busses; i++)
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if (reg == (fdt_addr_t)(uintptr_t)i2c_bus[i].regs)
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return i;
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debug("%s: Can't find any matched I2C bus\n", __func__);
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return -1;
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}
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int i2c_reset_port_fdt(const void *blob, int node)
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{
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struct s3c24x0_i2c_bus *i2c;
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int bus;
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bus = i2c_get_bus_num_fdt(blob, node);
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if (bus < 0) {
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printf("could not get bus for node %d\n", node);
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return -1;
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}
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i2c = get_bus(bus);
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if (!i2c) {
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printf("get_bus() failed for node node %d\n", node);
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return -1;
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}
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i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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return 0;
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}
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#endif
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/*
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* Verify the whether I2C ACK was received or not
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*
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* @param i2c pointer to I2C register base
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* @param buf array of data
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* @param len length of data
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* return I2C_OK when transmission done
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* I2C_NACK otherwise
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*/
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static int i2c_send_verify(struct s3c24x0_i2c *i2c, unsigned char buf[],
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unsigned char len)
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{
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int i, result = I2C_OK;
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if (IsACK(i2c)) {
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for (i = 0; (i < len) && (result == I2C_OK); i++) {
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writel(buf[i], &i2c->iicds);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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if (result == I2C_OK && !IsACK(i2c))
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result = I2C_NACK;
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}
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} else {
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result = I2C_NACK;
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}
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return result;
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}
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void i2c_init(int speed, int slaveadd)
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{
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struct s3c24x0_i2c_bus *i2c;
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struct exynos5_gpio_part1 *gpio;
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int i;
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uint32_t x;
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/* By default i2c channel 0 is the current bus */
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g_current_bus = 0;
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i2c = get_bus(g_current_bus);
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if (!i2c)
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return;
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i2c_bus_init(i2c, g_current_bus);
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/* wait for some time to give previous transfer a chance to finish */
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i = I2C_INIT_TIMEOUT_MS * 20;
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while ((readl(&i2c->regs->iicstat) & I2CSTAT_BSY) && (i > 0)) {
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udelay(50);
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i--;
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}
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gpio = exynos_get_base_gpio1();
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/* FIXME(dhendrix): cannot use nested macro (compilation failure) */
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// writel((readl(&gpio->b3.con) & ~0x00FF) | 0x0022, &gpio->b3.con);
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x = readl(&gpio->b3.con);
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writel((x & ~0x00FF) | 0x0022, &gpio->b3.con);
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i2c_ch_init(i2c->regs, speed, slaveadd);
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}
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/*
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* Send a STOP event and wait for it to have completed
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*
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* @param mode If it is a master transmitter or receiver
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* @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise
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*/
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static int i2c_send_stop(struct s3c24x0_i2c *i2c, int mode)
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{
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int timeout;
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/* Setting the STOP event to fire */
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writel(mode | I2C_TXRX_ENA, &i2c->iicstat);
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ReadWriteByte(i2c);
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/* Wait for the STOP to send and the bus to go idle */
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for (timeout = I2C_STOP_TIMEOUT_US; timeout > 0; timeout -= 5) {
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if (!(readl(&i2c->iicstat) & I2CSTAT_BSY))
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return I2C_OK;
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udelay(5);
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}
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return I2C_NOK_TOUT;
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}
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/*
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* cmd_type is 0 for write, 1 for read.
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*
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* addr_len can take any value from 0-255, it is only limited
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* by the char, we could make it larger if needed. If it is
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* 0 we skip the address write cycle.
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*/
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static int i2c_transfer(struct s3c24x0_i2c *i2c,
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unsigned char cmd_type,
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unsigned char chip,
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unsigned char addr[],
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unsigned char addr_len,
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unsigned char data[],
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unsigned short data_len)
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{
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int i, result, stop_bit_result;
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uint32_t x;
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if (data == 0 || data_len == 0) {
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/* Don't support data transfer of no length or to address 0 */
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debug("i2c_transfer: bad call\n");
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return I2C_NOK;
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}
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/* Check I2C bus idle */
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i = I2C_IDLE_TIMEOUT_MS * 20;
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while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
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udelay(50);
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i--;
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}
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if (readl(&i2c->iicstat) & I2CSTAT_BSY) {
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||||
debug("%s: bus busy\n", __func__);
|
||||
return I2C_NOK_TOUT;
|
||||
}
|
||||
|
||||
/* FIXME(dhendrix): cannot use nested macro (compilation failure) */
|
||||
//writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
|
||||
x = readl(&i2c->iiccon);
|
||||
writel(x | I2CCON_ACKGEN, &i2c->iiccon);
|
||||
|
||||
if (addr && addr_len) {
|
||||
writel(chip, &i2c->iicds);
|
||||
/* send START */
|
||||
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
|
||||
&i2c->iicstat);
|
||||
if (WaitForXfer(i2c) == I2C_OK)
|
||||
result = i2c_send_verify(i2c, addr, addr_len);
|
||||
else
|
||||
result = I2C_NACK;
|
||||
} else
|
||||
result = I2C_NACK;
|
||||
|
||||
switch (cmd_type) {
|
||||
case I2C_WRITE:
|
||||
if (result == I2C_OK)
|
||||
result = i2c_send_verify(i2c, data, data_len);
|
||||
else {
|
||||
writel(chip, &i2c->iicds);
|
||||
/* send START */
|
||||
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
|
||||
&i2c->iicstat);
|
||||
if (WaitForXfer(i2c) == I2C_OK)
|
||||
result = i2c_send_verify(i2c, data, data_len);
|
||||
}
|
||||
|
||||
if (result == I2C_OK)
|
||||
result = WaitForXfer(i2c);
|
||||
|
||||
stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MT);
|
||||
break;
|
||||
|
||||
case I2C_READ:
|
||||
{
|
||||
int was_ok = (result == I2C_OK);
|
||||
|
||||
writel(chip, &i2c->iicds);
|
||||
/* resend START */
|
||||
writel(I2C_MODE_MR | I2C_TXRX_ENA |
|
||||
I2C_START_STOP, &i2c->iicstat);
|
||||
ReadWriteByte(i2c);
|
||||
result = WaitForXfer(i2c);
|
||||
|
||||
if (was_ok || IsACK(i2c)) {
|
||||
i = 0;
|
||||
while ((i < data_len) && (result == I2C_OK)) {
|
||||
/* disable ACK for final READ */
|
||||
if (i == data_len - 1) {
|
||||
/* FIXME(dhendrix): nested macro */
|
||||
#if 0
|
||||
writel(readl(&i2c->iiccon) &
|
||||
~I2CCON_ACKGEN,
|
||||
&i2c->iiccon);
|
||||
#endif
|
||||
x = readl(&i2c->iiccon) & ~I2CCON_ACKGEN;
|
||||
writel(x, &i2c->iiccon);
|
||||
}
|
||||
ReadWriteByte(i2c);
|
||||
result = WaitForXfer(i2c);
|
||||
data[i] = readl(&i2c->iicds);
|
||||
i++;
|
||||
}
|
||||
} else {
|
||||
result = I2C_NACK;
|
||||
}
|
||||
|
||||
stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MR);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
debug("i2c_transfer: bad call\n");
|
||||
result = stop_bit_result = I2C_NOK;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the transmission went fine, then only the stop bit was left to
|
||||
* fail. Otherwise, the real failure we're interested in came before
|
||||
* that, during the actual transmission.
|
||||
*/
|
||||
return (result == I2C_OK) ? stop_bit_result : result;
|
||||
}
|
||||
|
||||
int i2c_probe(uchar chip)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c;
|
||||
uchar buf[1];
|
||||
int ret;
|
||||
|
||||
i2c = get_bus(g_current_bus);
|
||||
if (!i2c)
|
||||
return -1;
|
||||
buf[0] = 0;
|
||||
|
||||
/*
|
||||
* What is needed is to send the chip address and verify that the
|
||||
* address was <ACK>ed (i.e. there was a chip at that address which
|
||||
* drove the data line low).
|
||||
*/
|
||||
if (board_i2c_claim_bus(i2c->node)) {
|
||||
debug("I2C cannot claim bus %d\n", i2c->bus_num);
|
||||
return -1;
|
||||
}
|
||||
ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
|
||||
board_i2c_release_bus(i2c->node);
|
||||
|
||||
return ret != I2C_OK;
|
||||
}
|
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c;
|
||||
uchar xaddr[4];
|
||||
int ret;
|
||||
|
||||
if (alen > 4) {
|
||||
debug("I2C read: addr len %d not supported\n", alen);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (alen > 0) {
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
||||
* address and the extra bits end up in the "chip address"
|
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
||||
* four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to
|
||||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
if (alen > 0)
|
||||
chip |= ((addr >> (alen * 8)) &
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
i2c = get_bus(g_current_bus);
|
||||
if (!i2c)
|
||||
return -1;
|
||||
if (board_i2c_claim_bus(i2c->node)) {
|
||||
debug("I2C cannot claim bus %d\n", i2c->bus_num);
|
||||
return -1;
|
||||
}
|
||||
ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen],
|
||||
alen, buffer, len);
|
||||
board_i2c_release_bus(i2c->node);
|
||||
if (ret) {
|
||||
debug("I2c read: failed %d\n", ret);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c;
|
||||
uchar xaddr[4];
|
||||
int ret;
|
||||
|
||||
if (alen > 4) {
|
||||
debug("I2C write: addr len %d not supported\n", alen);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (alen > 0) {
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
}
|
||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
||||
* address and the extra bits end up in the "chip address"
|
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
||||
* four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to
|
||||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
if (alen > 0)
|
||||
chip |= ((addr >> (alen * 8)) &
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
i2c = get_bus(g_current_bus);
|
||||
if (!i2c)
|
||||
return -1;
|
||||
if (board_i2c_claim_bus(i2c->node)) {
|
||||
debug("I2C cannot claim bus %d\n", i2c->bus_num);
|
||||
return -1;
|
||||
}
|
||||
ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen],
|
||||
alen, buffer, len);
|
||||
board_i2c_release_bus(i2c->node);
|
||||
|
||||
return ret != 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _S3C24X0_I2C_H
|
||||
#define _S3C24X0_I2C_H
|
||||
|
||||
/* FIXME: gross hack */
|
||||
#include "cpu/samsung/exynos5250/periph.h"
|
||||
|
||||
struct s3c24x0_i2c {
|
||||
u32 iiccon;
|
||||
u32 iicstat;
|
||||
u32 iicadd;
|
||||
u32 iicds;
|
||||
u32 iiclc;
|
||||
};
|
||||
|
||||
struct s3c24x0_i2c_bus {
|
||||
int node; /* device tree node */
|
||||
int bus_num; /* i2c bus number */
|
||||
struct s3c24x0_i2c *regs;
|
||||
enum periph_id id;
|
||||
};
|
||||
#endif /* _S3C24X0_I2C_H */
|
||||
Loading…
Reference in New Issue