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mb/intel/mtlrvp: Enable PCIe port 8 for WLAN 

This patch enables PCIe port for WLAN as per mtlrvp schematics

BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WLAN module gets
is enumerated as part of lspci in AP console.

ae:00.0 Wireless controller [0d40]: Intel Corporation XMM7360 LTE
Advanced Modem (rev 01)

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72778
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Harsha B R 2023-02-04 10:35:50 +05:30 committed by Sridhar Siricilla
parent 05ca3d18a8
commit 453805ceb9
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -87,6 +87,14 @@ chip soc/intel/meteorlake
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
}" }"
end # WWAN end # WWAN
device ref pcie_rp8 on
# Enable PCH PCIE RP 8 using CLK 5
register "pcie_rp[PCIE_RP(8)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
}"
end # WLAN
device ref pcie_rp10 on device ref pcie_rp10 on
# Enable SSD Gen4 PCIE 10 using CLK 8 # Enable SSD Gen4 PCIE 10 using CLK 8
register "pcie_rp[PCIE_RP(10)]" = "{ register "pcie_rp[PCIE_RP(10)]" = "{