intel/fsp_baytrail: Fix SMM/SMI

With SMM enabled the boot stopped while patching up global NVS in DSDT.
The cause is that both CPUs are assigned the same SMBASE address.
So update the "cpu_smm_do_relocation()" function so that each
CPU gets a different SMBASE address

Based on rmodule work that wasn't propagated to the FSP
version: commit 3eb8eb7eba

Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b
Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com>
Reviewed-on: http://review.coreboot.org/7026
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kayalvizhi Dhandapani 2014-10-07 14:34:01 -04:00 committed by Marc Jones
parent 2c0f46afbb
commit 454625c5cf
3 changed files with 13 additions and 3 deletions

View File

@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail
register "SataMode" = "SATA_MODE_AHCI" register "SataMode" = "SATA_MODE_AHCI"
register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" register "MrcInitTsegSize" = "TSEG_SIZE_8_MB"
register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"

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@ -31,12 +31,16 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32
select DYNAMIC_CBMEM select DYNAMIC_CBMEM
select HAVE_SMI_HANDLER
select HAVE_HARD_RESET select HAVE_HARD_RESET
select MMCONF_SUPPORT select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES select RELOCATABLE_MODULES
select PARALLEL_MP select PARALLEL_MP
select REG_SCRIPT select REG_SCRIPT
select SMM_MODULES
select SMM_TSEG
select BAYTRAIL_SMM
select SMP select SMP
select SPI_FLASH select SPI_FLASH
select SSE2 select SSE2

View File

@ -148,14 +148,20 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params)
runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); runtime->apic_id_to_cpu[i] = mp_get_apic_id(i);
} }
static void asmlinkage static void asmlinkage cpu_smm_do_relocation(void *arg)
cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime)
{ {
#ifndef CONFIG_MAX_CPUS #ifndef CONFIG_MAX_CPUS
#error CONFIG_MAX_CPUS must be set. #error CONFIG_MAX_CPUS must be set.
#endif #endif
msr_t smrr; msr_t smrr;
em64t100_smm_state_save_area_t *smm_state; em64t100_smm_state_save_area_t *smm_state;
const struct smm_module_params *p;
const struct smm_runtime *runtime;
int cpu;
p = arg;
runtime = p->runtime;
cpu = p->cpu;
if (cpu >= CONFIG_MAX_CPUS) { if (cpu >= CONFIG_MAX_CPUS) {
printk(BIOS_CRIT, printk(BIOS_CRIT,