AMD K8 boards’ `romstage.c`: Spell sync*hr*onize correctly

Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5101
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -197,7 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	//do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synconize FID/VID
+//        init_timer(); // Need to use TMICT to synchronize FID/VID
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/asus/m2n-e/romstage.c

@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* TODO: FIDVID */
 
-	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+	init_timer(); /* Need to use TMICT to synchronize FID/VID. */
 
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         //do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synconize FID/VID
+//        init_timer(); // Need to use TMICT to synchronize FID/VID
 
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/gigabyte/m57sli/romstage.c

@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 #endif
 
-	init_timer(); // Need to use TMICT to synconize FID/VID
+	init_timer(); // Need to use TMICT to synchronize FID/VID
 
         needs_reset |= optimize_link_coherent_ht();
         needs_reset |= optimize_link_incoherent_ht(sysinfo);

src/mainboard/hp/dl145_g3/romstage.c

@@ -205,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	//do we need apci timer, tsc...., only debug need it for better output
 	/* all ap stopped? */
-	// init_timer(); // Need to use TMICT to synconize FID/VID
+	// init_timer(); // Need to use TMICT to synchronize FID/VID
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	//do we need apci timer, tsc...., only debug need it for better output
 	/* all ap stopped? */
-//	init_timer(); // Need to use TMICT to synconize FID/VID
+//	init_timer(); // Need to use TMICT to synchronize FID/VID
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);

src/mainboard/iwill/dk8_htx/romstage.c

@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	//do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
-        init_timer(); // Need to use TMICT to synconize FID/VID
+        init_timer(); // Need to use TMICT to synchronize FID/VID
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
 #if 0

src/mainboard/iwill/dk8s2/romstage.c

@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	//do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
-        init_timer(); // Need to use TMICT to synconize FID/VID
+        init_timer(); // Need to use TMICT to synchronize FID/VID
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
 #if 0

src/mainboard/iwill/dk8x/romstage.c

@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	//do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
-        init_timer(); // Need to use TMICT to synconize FID/VID
+        init_timer(); // Need to use TMICT to synchronize FID/VID
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
 #if 0

src/mainboard/msi/ms7260/romstage.c

@@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 #endif
 
-	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+	init_timer(); /* Need to use TMICT to synchronize FID/VID. */
 
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);

src/mainboard/msi/ms9185/romstage.c

@@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        //do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synconize FID/VID
+//        init_timer(); // Need to use TMICT to synchronize FID/VID
 
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/msi/ms9282/romstage.c

@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+	init_timer(); /* Need to use TMICT to synchronize FID/VID. */
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -203,7 +203,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	msr=rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
-	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+	init_timer(); /* Need to use TMICT to synchronize FID/VID. */
 
 	wants_reset = mcp55_early_setup_x();
 

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 #endif
 
-	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+	init_timer(); /* Need to use TMICT to synchronize FID/VID. */
 
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);

src/mainboard/supermicro/h8dme/romstage.c

@@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 #endif
 
-	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+	init_timer(); /* Need to use TMICT to synchronize FID/VID. */
 
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);

src/mainboard/supermicro/h8dmr/romstage.c

@@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 #endif
 
-	init_timer(); // Need to use TMICT to synconize FID/VID
+	init_timer(); // Need to use TMICT to synchronize FID/VID
 
         needs_reset |= optimize_link_coherent_ht();
         needs_reset |= optimize_link_incoherent_ht(sysinfo);

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	       msr.hi, msr.lo);
 #endif
 
-	init_timer(); // Need to use TMICT to synconize FID/VID
+	init_timer(); // Need to use TMICT to synchronize FID/VID
 
 	wants_reset = mcp55_early_setup_x();
 

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -263,7 +263,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
-	init_timer(); // Need to use TMICT to synconize FID/VID
+	init_timer(); // Need to use TMICT to synchronize FID/VID
 
  wants_reset = mcp55_early_setup_x();
 

src/mainboard/tyan/s2912/romstage.c

@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 #endif
 
-	init_timer(); // Need to use TMICT to synconize FID/VID
+	init_timer(); // Need to use TMICT to synchronize FID/VID
 
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
-	init_timer(); // Need to use TMICT to synconize FID/VID
+	init_timer(); // Need to use TMICT to synchronize FID/VID
 
 	wants_reset = mcp55_early_setup_x();