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intel/minnowmax: Enable all PCIe ports 

A recently announced Turbot system populates two Ethernet
controllers.  Enable the remaining disabled PCIe port.

Also add a clarifying comment regarding the port associated
with Function 0.  Coreboot must not be allowed to disable the
function which breaks PCI compatibility.

Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16429
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2016-09-02 16:10:58 -06:00 committed by Martin Roth
parent 297c559562
commit 4551bf6dbf
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/intel/minnowmax/devicetree.cb
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@ -76,8 +76,8 @@ chip soc/intel/fsp_baytrail
device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
device pci 1a.0 on end # 8086 0F18 - TXE - device pci 1a.0 on end # 8086 0F18 - TXE -
device pci 1b.0 off end # 8086 0F04 - HD Audio - device pci 1b.0 off end # 8086 0F04 - HD Audio -
device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on
device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models)
device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime