hatch: Create sushi variant

Create the sushi variant of the hatch reference
board by copying the template files to a new directory named
for the variant.

(Auto-Generated by create_coreboot_variant.sh version 3.0.0).

BUG=None
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_SUSHI

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie900d09ff55e695527eafe68a5a75cd4a0b6d340
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Paul Fagerburg 2020-03-26 16:14:58 -06:00 committed by Martin Roth
parent eb30e1a9aa
commit 4554942c8c
7 changed files with 85 additions and 0 deletions

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@ -103,6 +103,7 @@ config MAINBOARD_PART_NUMBER
default "Nightfury" if BOARD_GOOGLE_NIGHTFURY
default "Puff" if BOARD_GOOGLE_PUFF
default "Stryke" if BOARD_GOOGLE_STRYKE
default "Sushi" if BOARD_GOOGLE_SUSHI
config OVERRIDE_DEVICETREE
string
@ -128,6 +129,7 @@ config VARIANT_DIR
default "nightfury" if BOARD_GOOGLE_NIGHTFURY
default "puff" if BOARD_GOOGLE_PUFF
default "stryke" if BOARD_GOOGLE_STRYKE
default "sushi" if BOARD_GOOGLE_SUSHI
config VBOOT
select HAS_RECOVERY_MRC_CACHE

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@ -75,3 +75,8 @@ config BOARD_GOOGLE_STRYKE
bool "-> Stryke"
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_16384
config BOARD_GOOGLE_SUSHI
bool "-> Sushi"
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_16384

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@ -0,0 +1,13 @@
## This file is part of the coreboot project.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
SPD_SOURCES =

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@ -0,0 +1,14 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/dptf.asl>

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@ -0,0 +1,19 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef VARIANT_EC_H
#define VARIANT_EC_H
#include <baseboard/ec.h>
#endif

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@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
/* Memory configuration board straps */
/* Copied from baseboard and may need to change for the new variant. */
#define GPIO_MEM_CONFIG_0 GPP_F20
#define GPIO_MEM_CONFIG_1 GPP_F21
#define GPIO_MEM_CONFIG_2 GPP_F11
#define GPIO_MEM_CONFIG_3 GPP_F22
#endif

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@ -0,0 +1,6 @@
chip soc/intel/cannonlake
device domain 0 on
end
end