hatch: Create sushi variant
Create the sushi variant of the hatch reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 3.0.0). BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_SUSHI Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Ie900d09ff55e695527eafe68a5a75cd4a0b6d340 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -103,6 +103,7 @@ config MAINBOARD_PART_NUMBER
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default "Nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "Nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "Puff" if BOARD_GOOGLE_PUFF
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default "Puff" if BOARD_GOOGLE_PUFF
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default "Stryke" if BOARD_GOOGLE_STRYKE
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default "Stryke" if BOARD_GOOGLE_STRYKE
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default "Sushi" if BOARD_GOOGLE_SUSHI
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config OVERRIDE_DEVICETREE
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config OVERRIDE_DEVICETREE
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string
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string
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@ -128,6 +129,7 @@ config VARIANT_DIR
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default "nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "puff" if BOARD_GOOGLE_PUFF
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default "puff" if BOARD_GOOGLE_PUFF
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default "stryke" if BOARD_GOOGLE_STRYKE
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default "stryke" if BOARD_GOOGLE_STRYKE
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default "sushi" if BOARD_GOOGLE_SUSHI
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config VBOOT
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config VBOOT
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select HAS_RECOVERY_MRC_CACHE
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select HAS_RECOVERY_MRC_CACHE
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@ -75,3 +75,8 @@ config BOARD_GOOGLE_STRYKE
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bool "-> Stryke"
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bool "-> Stryke"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_16384
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select BOARD_ROMSIZE_KB_16384
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config BOARD_GOOGLE_SUSHI
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bool "-> Sushi"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_16384
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@ -0,0 +1,13 @@
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## This file is part of the coreboot project.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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SPD_SOURCES =
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@ -0,0 +1,14 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,19 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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/* Memory configuration board straps */
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/* Copied from baseboard and may need to change for the new variant. */
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#define GPIO_MEM_CONFIG_0 GPP_F20
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#define GPIO_MEM_CONFIG_1 GPP_F21
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#define GPIO_MEM_CONFIG_2 GPP_F11
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#define GPIO_MEM_CONFIG_3 GPP_F22
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#endif
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@ -0,0 +1,6 @@
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chip soc/intel/cannonlake
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device domain 0 on
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end
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end
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