From 455d7b74abdcc05ead46e1b4ca0f969df4f9a025 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 4 Dec 2020 01:59:15 +0100 Subject: [PATCH] soc/amd/picasso/tsc: fix clock divisor range check The CPU core clock divisor ID needs to be in the range from 8 to 0x30 including both numbers. TEST=Compared with Picasso's PPR #55570 Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/tsc_freq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index 8a541fc4a2..55c86653ce 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -33,7 +33,7 @@ unsigned long tsc_freq_mhz(void) if (!cpudid) { mhz = TSC_DEFAULT_FREQ_MHZ; printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz); - } else if ((cpudid >= 8) && (cpudid < 0x3c)) { + } else if ((cpudid >= 8) && (cpudid <= 0x30)) { mhz = (200 * cpufid) / cpudid; } else { mhz = 25 * cpufid;