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mb/asrock/b85m_pro4: Expand Super I/O comments

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Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42399
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-06-15 16:58:27 +02:00
parent fb767d8397
commit 456852f437
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/asrock/b85m_pro4/devicetree.cb
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@ -60,18 +60,18 @@ chip northbridge/intel/haswell
io 0x60 = 0x0378 io 0x60 = 0x0378
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
irq 0xf0 = 0x3b irq 0xf0 = 0x3b # + ECP and EPP 1.9
end end
device pnp 2e.2 on # UART A device pnp 2e.2 on # UART A
io 0x60 = 0x03f8 io 0x60 = 0x03f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 off end # UART B, IR device pnp 2e.3 off end # UART B, IR
device pnp 2e.5 on # PS/2 KBC device pnp 2e.5 on # PS/2 Keyboard/Mouse
io 0x60 = 0x0060 io 0x60 = 0x0060
io 0x62 = 0x0064 io 0x62 = 0x0064
irq 0x70 = 1 # + Keyboard irq 0x70 = 1 # + Keyboard IRQ
irq 0x72 = 12 # + Mouse irq 0x72 = 12 # + Mouse IRQ (unused)
end end
device pnp 2e.6 off end # CIR device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GPIO8 device pnp 2e.7 off end # GPIO8
@ -100,8 +100,8 @@ chip northbridge/intel/haswell
irq 0xf0 = 0x20 irq 0xf0 = 0x20
end end
device pnp 2e.b on # HWM, LED device pnp 2e.b on # HWM, LED
irq 0x30 = 0xe1 irq 0x30 = 0xe1 # + Fan RPM sense pins
io 0x60 = 0x0290 io 0x60 = 0x0290 # + HWM base address
end end
device pnp 2e.d off end # VID device pnp 2e.d off end # VID
device pnp 2e.e off end # CIR wake-up device pnp 2e.e off end # CIR wake-up