superio/nuvoton: Add support for NPCD378
The NPCD378 can be found on at least: * HP Compaq 8200 * HP Compaq 8300 The datasheet is not publicly available, as HP implements lots of custom hardware. Add basic support for it, based on HP Compaq 8200. The first eight LDNs seem to be standard nuvoton compatible, except for LDN4, which is used to control front LED and power in ACPI S3. LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's IOBASE with a size of 0x100 bytes. The HWM consists of 16 pages with each holding 0xff bytes. The pages can be selected by writing the page index to IOBASE + 0xff. TODO: Reverse engineer the HWM to support fan control. WARNING: The remaining LDNs have been guessed and might be wrong! The serial has been tested and is working. Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25384 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
Patrick Rudolph
parent
3337497d2a
commit
4576600dd2
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@ -25,3 +25,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
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subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776
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subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
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subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d
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subdirs-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += npcd378
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@ -0,0 +1,18 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SUPERIO_NUVOTON_NPCD378
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bool
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select SUPERIO_NUVOTON_COMMON_ROMSTAGE
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@ -0,0 +1,17 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += superio.c
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@ -0,0 +1,168 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
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* Copyright (C) 2013, 2016 secunet Security Networks AG
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* Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the NPCD378 SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* 0x2 SP1 Implemented, untested
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* 0x5 KBCK Implemented, untested
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME NPCD378
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("Nuvoton NPCD378 Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8,
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}
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IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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ACT1, 1, /* Logical device activation */
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ACT2, 1, /* Logical device activation */
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ACT3, 1, /* Logical device activation */
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ACT4, 1, /* Logical device activation */
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ACT5, 1, /* Logical device activation */
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ACT6, 1, /* Logical device activation */
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ACT7, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x64),
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PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */
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PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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Offset (0x72),
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PNP_IRQ1, 8, /* Second IRQ */
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}
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Method (_CRS)
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{
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/* Announce the used I/O ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#undef PNP_EXIT_SPECIAL_REG
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#undef PNP_EXIT_SPECIAL_VAL
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x87
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#define PNP_EXIT_MAGIC_1ST 0xaa
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#include <superio/acpi/pnp_config.asl>
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#ifdef SUPERIO_SHOW_LPT
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#undef PNP_DEVICE_ACTIVE
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#define PNP_DEVICE_ACTIVE ACT3
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#define SUPERIO_PNP_LDN 1
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#include <superio/acpi/pnp_generic.asl>
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#endif
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#ifdef SUPERIO_SHOW_SP1
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef SUPERIO_SHOW_SP2
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 3
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef SUPERIO_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_PS2LDN 5
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#define SUPERIO_KBC_LDN 6
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#ifdef SUPERIO_SHOW_GPIO
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#undef PNP_DEVICE_ACTIVE
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#define PNP_DEVICE_ACTIVE ACT3
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#define SUPERIO_PNP_LDN 8
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#include <superio/acpi/pnp_generic.asl>
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#endif
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}
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@ -0,0 +1,37 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SUPERIO_NUVOTON_NPCD378_H
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#define SUPERIO_NUVOTON_NPCD378_H
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/* Logical Device Numbers (LDN). */
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/* Default Nuvoton hardware: */
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#define NPCD378_FDC 0x00 /* Floppy */
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#define NPCD378_PP 0x01 /* Parallel port */
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#define NPCD378_SP1 0x02 /* Com1 */
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#define NPCD378_SP2 0x03 /* Com2 & IR */
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#define NPCD378_PWR 0x04 /* LED and PWR button control */
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#define NPCD378_AUX 0x05 /* PS/2 mouse */
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#define NPCD378_KBC 0x06 /* PS/2 keyboard */
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/* The following is guessed based on observation and might be wrong: */
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#define NPCD378_WDT1 0x07
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#define NPCD378_HWM 0x08 /* HWM: 16 pages with each 255 byte */
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#define NPCD378_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */
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#define NPCD378_I2C 0x15 /* Provides 35Khz at IOBASE + 0x9 */
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#define NPCD378_SUSPEND 0x1c /* Suspend control ? */
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#define NPCD378_GPIOA 0x1e
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#endif /* SUPERIO_NUVOTON_NPCD378_H */
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@ -0,0 +1,87 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <pc80/keyboard.h>
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#include <stdlib.h>
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#include <superio/conf_mode.h>
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#include "npcd378.h"
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static void npcd378_init(struct device *dev)
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{
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if (!dev->enabled)
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return;
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switch (dev->path.pnp.device) {
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/* TODO: Might potentially need code for HWM or FDC etc. */
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case NPCD378_KBC:
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pc_keyboard_init(PROBE_AUX_DEVICE);
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break;
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}
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = npcd378_init,
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.ops_pnp_mode = &pnp_conf_mode_8787_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ &ops, NPCD378_FDC, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, },
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{ &ops, NPCD378_PP, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, },
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{ &ops, NPCD378_SP1, PNP_IO0|PNP_IRQ0, 0x0ff8, },
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{ &ops, NPCD378_SP2, PNP_IO0|PNP_IRQ0, 0x0ff8, },
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{ &ops, NPCD378_PWR, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0|
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PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|
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PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE,
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0x0ff8, 0x0ff8},
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{ &ops, NPCD378_AUX, PNP_IRQ0, 0x0fff, 0x0fff, },
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{ &ops, NPCD378_KBC, PNP_IO0|PNP_IO1|PNP_IRQ0,
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0x0fff, 0x0fff, },
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{ &ops, NPCD378_WDT1, PNP_IO0|PNP_MSC8|PNP_MSC9|
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PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, 0x0ff8},
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{ &ops, NPCD378_HWM, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
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PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_IRQ0, 0x0ff8},
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{ &ops, NPCD378_GPIO_PP_OD, PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
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PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_MSC8|PNP_MSC9|PNP_MSCA|
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PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE},
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{ &ops, NPCD378_I2C, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0|
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PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|
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PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE,
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0x0ff8, 0x0ff8},
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{ &ops, NPCD378_SUSPEND, PNP_IO0, 0x0ff8 },
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{ &ops, NPCD378_GPIOA, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
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PNP_MSC4, 0x0ff8},
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_nuvoton_npcd378_ops = {
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CHIP_NAME("NUVOTON NPCD378 Super I/O")
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.enable_dev = enable_dev,
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};
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