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soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done 

This patch calls into the PMC IPC function that informs about PMC
enumeration.

Note: Alder Lake FSP Notify Phase 1 callback missed to send this PMC
IPC, hence, this patch is considered as an improvement over FSP Notify
Phase API.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS without any PMC IPC
error.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I43cfad25a5861c5aa5dae293ff42c9cefe862ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Subrata Banik 2022-04-29 14:22:18 +05:30 committed by Felix Held
parent a3146205c3
commit 4578914153
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/alderlake/lockdown.c
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@ -9,6 +9,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelpch/lockdown.h> #include <intelpch/lockdown.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <soc/pm.h> #include <soc/pm.h>
@ -36,6 +37,9 @@ static void pmc_lockdown_cfg(int chipset_lockdown)
setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
PM_CFG_XRAM_READ_DISABLE); PM_CFG_XRAM_READ_DISABLE);
} }
/* Send PMC IPC to inform about PCI enumeration done */
pmc_send_pci_enum_done();
} }
static void pch_lockdown_cfg(void) static void pch_lockdown_cfg(void)