Trivial fixups to get this board further along.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -183,10 +183,10 @@ default CONFIG_GDB_STUB=0
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default CONFIG_TTYS0_BAUD=115200
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#default CONFIG_TTYS0_BAUD=115200
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#default CONFIG_TTYS0_BAUD=57600
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#default CONFIG_TTYS0_BAUD=38400
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#default CONFIG_TTYS0_BAUD=19200
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default CONFIG_TTYS0_BAUD=19200
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#default CONFIG_TTYS0_BAUD=9600
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#default CONFIG_TTYS0_BAUD=4800
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#default CONFIG_TTYS0_BAUD=2400
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@ -13,14 +13,13 @@
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#include "lib/ramtest.c"
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#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
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#include "northbridge/intel/e7520/raminit.h"
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#include "superio/winbond/w83627hf/w83627hf.h"
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#include "superio/nsc/pc8374/pc8374_early_serial.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "debug.c"
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#include "watchdog.c"
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#include "reset.c"
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#include "s2850_fixups.c"
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#include "superio/winbond/w83627hf/w83627hf_early_init.c"
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#include "s1850_fixups.c"
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#include "northbridge/intel/e7520/memory_initialized.c"
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#include "cpu/x86/bist.h"
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@ -28,8 +27,7 @@
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#define SIO_GPIO_BASE 0x680
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#define SIO_XBUS_BASE 0x4880
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#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
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#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
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#define DEVPRES_CONFIG ( \
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DEVPRES_D0F0 | \
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@ -201,11 +199,9 @@ static void main(unsigned long bist)
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}
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}
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/* Setup the console */
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mainboard_set_ich5();
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bmc_foad();
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outb(0x87,0x2e);
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outb(0x87,0x2e);
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pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
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w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
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pc8374_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
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uart_init();
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console_init();
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@ -0,0 +1,40 @@
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#include <arch/romcc_io.h>
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static void mch_reset(void)
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{
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return;
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}
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static void mainboard_set_e7520_pll(unsigned bits)
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{
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return;
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}
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static void mainboard_set_e7520_leds(void)
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{
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return;
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}
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static void mainboard_set_ich5(void)
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{
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/* coma is 0x3f8 , comb is 0x2f8*/
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe0, 0x10);
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/* enable decoding of various devices */
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xe6, 0x140f);
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/* 1M flash */
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0);
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/* disable certain devices -- see data sheet -- this is from
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* dell settings via lspci
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* Note that they leave SMBUS disabled -- 8f6f.
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* we leave it enabled and visible in config space -- 8f66
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*/
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66);
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}
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@ -1,23 +0,0 @@
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#include <arch/romcc_io.h>
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static void mch_reset(void)
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{
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return;
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}
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static void mainboard_set_e7520_pll(unsigned bits)
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{
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return;
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}
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static void mainboard_set_e7520_leds(void)
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{
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return;
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}
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