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mb/google/volteer/var/malefor: Use auto-generated Makefile.inc using gen_part_id.go 

This change adds mem_list_variant.txt that contains the list of
memory parts used by malefor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:

Part: K4U6E3S4AA-MGCL
Byte#    Current     New         Explanation
6        0x95        0x94        Signal loading is not used by
                                 MRC. Bits 1:0 set to 0.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.

BUG=b:155239397,b:147321551

Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2020-05-20 23:09:51 -07:00 committed by Patrick Georgi
parent ae7ebcb316
commit 459655abe7
3 changed files with 8 additions and 0 deletions
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5
src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc Normal file
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@ -0,0 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-or-later
## This is an auto-generated file. Do not edit!!
SPD_SOURCES =
SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL

2
src/mainboard/google/volteer/variants/malefor/memory/dram_id.generated.txt Normal file
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@ -0,0 +1,2 @@
DRAM Part Name ID to assign
K4U6E3S4AA-MGCL 0 (0000)

1
src/mainboard/google/volteer/variants/malefor/memory/mem_list_variant.txt Normal file
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@ -0,0 +1 @@
K4U6E3S4AA-MGCL