soc/intel/cpulib: Factor out IA32_PERF_CTL (0x199) MSR code
This patch replaces multiple IA32_PERF_CTL programming with single helper function. TEST=Build and boot WHL and CML platform. Change-Id: I212daa61aa11191dd832630461b517d3dbedd6e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -73,6 +73,13 @@ int cpu_config_tdp_levels(void)
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return (platform_info.hi >> 1) & 3;
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}
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static void set_perf_control_msr(msr_t msr)
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{
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wrmsr(IA32_PERF_CTL, msr);
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printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
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((msr.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
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}
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/*
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* TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the
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* factory configured values for of 1-core, 2-core, 3-core
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@ -93,9 +100,7 @@ void cpu_set_p_state_to_turbo_ratio(void)
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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perf_ctl.hi = 0;
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wrmsr(IA32_PERF_CTL, perf_ctl);
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printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
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((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
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set_perf_control_msr(perf_ctl);
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}
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/*
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@ -113,9 +118,7 @@ void cpu_set_p_state_to_nominal_tdp_ratio(void)
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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perf_ctl.hi = 0;
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wrmsr(IA32_PERF_CTL, perf_ctl);
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printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
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((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
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set_perf_control_msr(perf_ctl);
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}
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/*
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@ -133,9 +136,7 @@ void cpu_set_p_state_to_max_non_turbo_ratio(void)
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perf_ctl.lo = msr.lo & 0xff00;
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perf_ctl.hi = 0;
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wrmsr(IA32_PERF_CTL, perf_ctl);
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printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
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((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
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set_perf_control_msr(perf_ctl);
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}
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/*
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@ -152,9 +153,8 @@ void cpu_set_p_state_to_min_clock_ratio(void)
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min_ratio = cpu_get_min_ratio();
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perf_ctl.lo = (min_ratio << 8) & 0xff00;
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perf_ctl.hi = 0;
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wrmsr(IA32_PERF_CTL, perf_ctl);
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printk(BIOS_DEBUG, "CPU: frequency set to %u MHz\n",
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(min_ratio * CONFIG_CPU_BCLK_MHZ));
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set_perf_control_msr(perf_ctl);
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}
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/*
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