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soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller 

- Correctly detect device 17h as the MMC 4.5 controller
- Support detection of the "old" MMC controller at device 10h

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Mate Kukri 2020-07-03 14:44:49 +02:00 committed by Patrick Georgi
parent 355d1c9870
commit 45b51e0180
6 changed files with 37 additions and 24 deletions
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3
src/mainboard/google/rambi/devicetree.cb
View File

@ -59,12 +59,13 @@ chip soc/intel/baytrail
device domain 0 on device domain 0 on
device pci 00.0 on end # SoC router device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX device pci 02.0 on end # GFX
device pci 10.0 off end # MMC
device pci 11.0 off end # SDIO device pci 11.0 off end # SDIO
device pci 12.0 on end # SD device pci 12.0 on end # SD
device pci 13.0 on end # SATA device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE device pci 15.0 on end # LPE
device pci 17.0 on end # MMC device pci 17.0 on end # MMC45
device pci 18.0 on end # SIO_DMA1 device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1 device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2 device pci 18.2 on end # I2C2

2
src/mainboard/google/rambi/irqroute.h
View File

@ -11,7 +11,7 @@
PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, D, E, F, G), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \

2
src/soc/intel/baytrail/emmc.c
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@ -52,5 +52,5 @@ static struct device_operations device_ops = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VENDOR_ID_INTEL,
.device = MMC_DEVID, .device = MMC45_DEVID,
}; };

13
src/soc/intel/baytrail/include/soc/pci_devs.h
View File

@ -13,6 +13,10 @@
#define GFX_DEV 0x2 #define GFX_DEV 0x2
#define GFX_FUNC 0 #define GFX_FUNC 0
/* MMC Port */
#define MMC_DEV 0x10
#define MMC_FUNC 0
/* SDIO Port */ /* SDIO Port */
#define SDIO_DEV 0x11 #define SDIO_DEV 0x11
#define SDIO_FUNC 0 #define SDIO_FUNC 0
@ -33,9 +37,9 @@
#define LPE_DEV 0x15 #define LPE_DEV 0x15
#define LPE_FUNC 0 #define LPE_FUNC 0
/* MMC Port */ /* MMC45 Port */
#define MMC_DEV 0x17 #define MMC45_DEV 0x17
#define MMC_FUNC 0 #define MMC45_FUNC 0
/* Serial IO 1 */ /* Serial IO 1 */
#define SIO1_DEV 0x18 #define SIO1_DEV 0x18
@ -103,6 +107,7 @@
#define SOC_DEVID 0x0f00 #define SOC_DEVID 0x0f00
#define GFX_DEVID 0x0f31 #define GFX_DEVID 0x0f31
#define MMC_DEVID 0x0f14
#define SDIO_DEVID 0x0f15 #define SDIO_DEVID 0x0f15
#define SD_DEVID 0x0f16 #define SD_DEVID 0x0f16
#define IDE1_DEVID 0x0f20 #define IDE1_DEVID 0x0f20
@ -111,7 +116,7 @@
#define AHCI2_DEVID 0x0f23 #define AHCI2_DEVID 0x0f23
#define XHCI_DEVID 0x0f35 #define XHCI_DEVID 0x0f35
#define LPE_DEVID 0x0f28 #define LPE_DEVID 0x0f28
#define MMC_DEVID 0x0f50 #define MMC45_DEVID 0x0f50
#define SIO_DMA1_DEVID 0x0f40 #define SIO_DMA1_DEVID 0x0f40
#define I2C1_DEVID 0x0f41 #define I2C1_DEVID 0x0f41
#define I2C2_DEVID 0x0f42 #define I2C2_DEVID 0x0f42

3
src/soc/intel/baytrail/include/soc/pm.h
View File

@ -66,9 +66,10 @@
# define HSUART1_DIS (1 << 3) # define HSUART1_DIS (1 << 3)
# define HSUART2_DIS (1 << 4) # define HSUART2_DIS (1 << 4)
# define SPI_DIS (1 << 5) # define SPI_DIS (1 << 5)
# define MMC_DIS (1 << 8)
# define SDIO_DIS (1 << 9) # define SDIO_DIS (1 << 9)
# define SD_DIS (1 << 10) # define SD_DIS (1 << 10)
# define MMC_DIS (1 << 11) # define MMC45_DIS (1 << 11)
# define HDA_DIS (1 << 12) # define HDA_DIS (1 << 12)
# define LPE_DIS (1 << 13) # define LPE_DIS (1 << 13)
# define OTG_DIS (1 << 14) # define OTG_DIS (1 << 14)

12
src/soc/intel/baytrail/southcluster.c
View File

@ -204,6 +204,9 @@ static void sc_disable_devfn(struct device *dev)
uint32_t mask2 = 0; uint32_t mask2 = 0;
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
case PCI_DEVFN(MMC_DEV, MMC_FUNC):
mask |= MMC_DIS;
break;
case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
mask |= SDIO_DIS; mask |= SDIO_DIS;
break; break;
@ -221,8 +224,8 @@ static void sc_disable_devfn(struct device *dev)
case PCI_DEVFN(LPE_DEV, LPE_FUNC): case PCI_DEVFN(LPE_DEV, LPE_FUNC):
mask |= LPE_DIS; mask |= LPE_DIS;
break; break;
case PCI_DEVFN(MMC_DEV, MMC_FUNC): case PCI_DEVFN(MMC45_DEV, MMC45_FUNC):
mask |= MMC_DIS; mask |= MMC45_DIS;
break; break;
case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC):
mask |= SIO_DMA1_DIS; mask |= SIO_DMA1_DIS;
@ -362,13 +365,16 @@ static int place_device_in_d3hot(struct device *dev)
* Work around this by hard coding the offset. * Work around this by hard coding the offset.
*/ */
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
case PCI_DEVFN(MMC_DEV, MMC_FUNC):
offset = 0x80;
break;
case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
offset = 0x80; offset = 0x80;
break; break;
case PCI_DEVFN(SD_DEV, SD_FUNC): case PCI_DEVFN(SD_DEV, SD_FUNC):
offset = 0x80; offset = 0x80;
break; break;
case PCI_DEVFN(MMC_DEV, MMC_FUNC): case PCI_DEVFN(MMC45_DEV, MMC45_FUNC):
offset = 0x80; offset = 0x80;
break; break;
case PCI_DEVFN(LPE_DEV, LPE_FUNC): case PCI_DEVFN(LPE_DEV, LPE_FUNC):