soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller
- Correctly detect device 17h as the MMC 4.5 controller - Support detection of the "old" MMC controller at device 10h Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -59,12 +59,13 @@ chip soc/intel/baytrail
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device domain 0 on
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device pci 00.0 on end # SoC router
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device pci 02.0 on end # GFX
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device pci 10.0 off end # MMC
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device pci 11.0 off end # SDIO
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device pci 12.0 on end # SD
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device pci 13.0 on end # SATA
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device pci 14.0 on end # XHCI
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device pci 15.0 on end # LPE
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device pci 17.0 on end # MMC
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device pci 17.0 on end # MMC45
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device pci 18.0 on end # SIO_DMA1
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device pci 18.1 on end # I2C1
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device pci 18.2 on end # I2C2
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@ -11,7 +11,7 @@
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
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@ -52,5 +52,5 @@ static struct device_operations device_ops = {
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static const struct pci_driver southcluster __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = MMC_DEVID,
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.device = MMC45_DEVID,
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};
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@ -13,6 +13,10 @@
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#define GFX_DEV 0x2
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#define GFX_FUNC 0
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/* MMC Port */
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#define MMC_DEV 0x10
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#define MMC_FUNC 0
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/* SDIO Port */
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#define SDIO_DEV 0x11
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#define SDIO_FUNC 0
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@ -33,9 +37,9 @@
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#define LPE_DEV 0x15
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#define LPE_FUNC 0
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/* MMC Port */
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#define MMC_DEV 0x17
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#define MMC_FUNC 0
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/* MMC45 Port */
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#define MMC45_DEV 0x17
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#define MMC45_FUNC 0
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/* Serial IO 1 */
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#define SIO1_DEV 0x18
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@ -103,6 +107,7 @@
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#define SOC_DEVID 0x0f00
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#define GFX_DEVID 0x0f31
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#define MMC_DEVID 0x0f14
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#define SDIO_DEVID 0x0f15
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#define SD_DEVID 0x0f16
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#define IDE1_DEVID 0x0f20
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@ -111,7 +116,7 @@
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#define AHCI2_DEVID 0x0f23
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#define XHCI_DEVID 0x0f35
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#define LPE_DEVID 0x0f28
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#define MMC_DEVID 0x0f50
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#define MMC45_DEVID 0x0f50
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#define SIO_DMA1_DEVID 0x0f40
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#define I2C1_DEVID 0x0f41
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#define I2C2_DEVID 0x0f42
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@ -66,9 +66,10 @@
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# define HSUART1_DIS (1 << 3)
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# define HSUART2_DIS (1 << 4)
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# define SPI_DIS (1 << 5)
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# define MMC_DIS (1 << 8)
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# define SDIO_DIS (1 << 9)
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# define SD_DIS (1 << 10)
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# define MMC_DIS (1 << 11)
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# define MMC45_DIS (1 << 11)
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# define HDA_DIS (1 << 12)
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# define LPE_DIS (1 << 13)
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# define OTG_DIS (1 << 14)
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@ -204,6 +204,9 @@ static void sc_disable_devfn(struct device *dev)
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uint32_t mask2 = 0;
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(MMC_DEV, MMC_FUNC):
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mask |= MMC_DIS;
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break;
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case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
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mask |= SDIO_DIS;
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break;
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@ -221,8 +224,8 @@ static void sc_disable_devfn(struct device *dev)
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case PCI_DEVFN(LPE_DEV, LPE_FUNC):
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mask |= LPE_DIS;
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break;
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case PCI_DEVFN(MMC_DEV, MMC_FUNC):
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mask |= MMC_DIS;
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case PCI_DEVFN(MMC45_DEV, MMC45_FUNC):
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mask |= MMC45_DIS;
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break;
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case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC):
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mask |= SIO_DMA1_DIS;
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@ -362,13 +365,16 @@ static int place_device_in_d3hot(struct device *dev)
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* Work around this by hard coding the offset.
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*/
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(MMC_DEV, MMC_FUNC):
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offset = 0x80;
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break;
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case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
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offset = 0x80;
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break;
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case PCI_DEVFN(SD_DEV, SD_FUNC):
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offset = 0x80;
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break;
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case PCI_DEVFN(MMC_DEV, MMC_FUNC):
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case PCI_DEVFN(MMC45_DEV, MMC45_FUNC):
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offset = 0x80;
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break;
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case PCI_DEVFN(LPE_DEV, LPE_FUNC):
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