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mb/intel/dg43gt: Make devicetree prettier 

Use lowercase for hex constants and align comments and register values.

Change-Id: Ib14906113e366a2a6f268fe8b8be32b1794fb344
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38077
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-01-01 21:44:21 +01:00 committed by Nico Huber
parent 221b894e7d
commit 45b5e03641
1 changed files with 40 additions and 42 deletions
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82
src/mainboard/intel/dg43gt/devicetree.cb
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@ -20,15 +20,15 @@ chip northbridge/intel/x4x # Northbridge
chip cpu/intel/socket_LGA775 chip cpu/intel/socket_LGA775
device lapic 0 on end device lapic 0 on end
end end
chip cpu/intel/model_1067x # CPU chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end device lapic 0xacac off end
end end
end end
device domain 0 on # PCI domain device domain 0 on # PCI domain
subsystemid 0x8086 0x0028 inherit subsystemid 0x8086 0x0028 inherit
device pci 0.0 on end # Host Bridge device pci 0.0 on end # Host Bridge
device pci 2.0 on end # Integrated graphics controller device pci 2.0 on end # Integrated graphics controller
device pci 2.1 on end # Integrated graphics controller 2 device pci 2.1 on end # Integrated graphics controller 2
device pci 3.0 off end # ME device pci 3.0 off end # ME
device pci 3.1 off end # ME device pci 3.1 off end # ME
chip southbridge/intel/i82801jx # Southbridge chip southbridge/intel/i82801jx # Southbridge
@ -40,54 +40,54 @@ chip northbridge/intel/x4x # Northbridge
register "sata_traffic_monitor" = "0" register "sata_traffic_monitor" = "0"
# Enable PCIe ports 0,2,3 as slots. # Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0xb" register "pcie_slot_implemented" = "0xb"
register "gen1_dec" = "0x00fc0601" register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0291" register "gen2_dec" = "0x00fc0291"
device pci 19.0 on end # GBE device pci 19.0 on end # GBE
device pci 1a.0 on end # USB device pci 1a.0 on end # USB
device pci 1a.1 on end # USB device pci 1a.1 on end # USB
device pci 1a.2 on end # USB device pci 1a.2 on end # USB
device pci 1a.7 on end # USB device pci 1a.7 on end # USB
device pci 1b.0 on end # Audio device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1 device pci 1c.0 on end # PCIe 1
device pci 1c.1 off end # PCIe 2 device pci 1c.1 off end # PCIe 2
device pci 1c.2 on end # PCIe 3 device pci 1c.2 on end # PCIe 3
device pci 1c.3 on end # PCIe 4 device pci 1c.3 on end # PCIe 4
device pci 1c.4 off end # PCIe 5 device pci 1c.4 off end # PCIe 5
device pci 1c.5 off end # PCIe 6 device pci 1c.5 off end # PCIe 6
device pci 1d.0 on end # USB device pci 1d.0 on end # USB
device pci 1d.1 on end # USB device pci 1d.1 on end # USB
device pci 1d.2 on end # USB device pci 1d.2 on end # USB
device pci 1d.7 on end # USB device pci 1d.7 on end # USB
device pci 1e.0 on end # PCI bridge device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # ISA bridge device pci 1f.0 on # LPC bridge
chip superio/winbond/w83627dhg # Super I/O chip superio/winbond/w83627dhg # Super I/O
device pnp 2e.0 on # Floppy device pnp 2e.0 on # Floppy
# GLOBAL # GLOBAL
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 on # Parallel port device pnp 2e.1 on # Parallel port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 5 irq 0x70 = 5
drq 0x74 = 4 drq 0x74 = 4
end end
device pnp 2e.2 on # COM 1 device pnp 2e.2 on # COM 1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 off end # COM 2 device pnp 2e.3 off end # COM 2
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
irq 0x70 = 1 irq 0x70 = 1
io 0x62 = 0x64 io 0x62 = 0x64
irq 0xf0 = 0x85 irq 0xf0 = 0x85
end end
device pnp 2e.6 off end # SPI device pnp 2e.6 off end # SPI
device pnp 2e.7 on end # GPIO 6 device pnp 2e.7 on end # GPIO 6
device pnp 2e.8 off end # WDTO# PLED device pnp 2e.8 off end # WDTO# PLED
device pnp 2e.9 off end # GPIO 2 device pnp 2e.9 off end # GPIO 2
device pnp 2e.109 on # GPIO 3 device pnp 2e.109 on # GPIO 3
@ -99,31 +99,29 @@ chip northbridge/intel/x4x # Northbridge
irq 0xe1 = 0x01 irq 0xe1 = 0x01
end end
device pnp 2e.a on # ACPI device pnp 2e.a on # ACPI
irq 0xe4 = 0x30 # power dram during S3 irq 0xe4 = 0x30 # power dram during S3
end end
device pnp 2e.b on # Hardware monitor device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290 io 0x60 = 0x290
end end
device pnp 2e.c off end # PECI, SST device pnp 2e.c off end # PECI, SST
end end
end end
device pci 1f.1 on end # PATA/IDE device pci 1f.1 on end # PATA/IDE
device pci 1f.2 on end # SATA device pci 1f.2 on end # SATA
device pci 1f.3 on # SMbus device pci 1f.3 on # SMBus
chip drivers/i2c/ck505 # SLG8XP549T chip drivers/i2c/ck505 # SLG8XP549T
register "mask" = "{ 0xff, 0xff, 0xff, register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
0xff, 0xff }" register "regs" = "{ 0x11, 0xd9, 0xff, 0xfd,
register "regs" = "{ 0x11, 0xd9, 0xff, 0xff, 0x00, 0x00, 0x06,
0xfd, 0xff, 0x00, 0x00, 0x10, 0x05, 0x01, 0x80, 0x0d }"
0x06, 0x10, 0x05, 0x01,
0x80, 0x0d }"
device i2c 69 on end device i2c 69 on end
end end
end end
device pci 1f.4 off end device pci 1f.4 off end
device pci 1f.5 on end # IDE device pci 1f.5 on end # IDE
device pci 1f.6 off end device pci 1f.6 off end
end end
end end