diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 067222440c..f5dc01910d 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -50,6 +50,7 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieClkSrcUsage[2]" = "8" register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[8]" = "1" # Mark unused SRCCLKREQs as so register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a93a38a830..1fa7d2fa5f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -120,11 +120,13 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[8]" = "1" # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "0" + register "PcieRpSlotImplemented[10]" = "1" # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" @@ -138,6 +140,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[6]" = "1" # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 8fdc0674db..808127f86d 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -15,6 +15,7 @@ chip soc/intel/tigerlake register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + register "PcieRpSlotImplemented[6]" = "1" # Disable SD Card PCIE 8 register "PcieRpEnable[7]" = "0" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 201983cc87..d01fdd6352 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -44,6 +44,10 @@ chip soc/intel/tigerlake register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpSlotImplemented[10]" = "1" # Enable RP LTR register "PcieRpLtrEnable[2]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d76c0f530c..c0adcc3f50 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -45,6 +45,10 @@ chip soc/intel/tigerlake register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpSlotImplemented[10]" = "1" # Enable PR LTR register "PcieRpLtrEnable[2]" = "1" diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 6bfe208e1e..fb559d284e 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -181,6 +181,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "0x08" register "PcieClkSrcClkReq[3]" = "3" + register "PcieRpSlotImplemented[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.1 off end # PCI Express Port 10 diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 75b0836050..ae91bdd005 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -285,6 +285,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[1]" = "7" register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 4 (SSD0) @@ -292,6 +293,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[8]" = "1" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD_PWR_EN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 880da1eee8..716afd4d0a 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -303,6 +303,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[10]" = "1" end device ref pch_espi on register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/system76/gaze16/variants/3050/overridetree.cb b/src/mainboard/system76/gaze16/variants/3050/overridetree.cb index 73520b5dc8..c26b7d2fed 100644 --- a/src/mainboard/system76/gaze16/variants/3050/overridetree.cb +++ b/src/mainboard/system76/gaze16/variants/3050/overridetree.cb @@ -62,6 +62,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[8]" = "7" register "PcieClkSrcClkReq[8]" = "8" + register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 9 (SSD1) @@ -69,6 +70,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" + register "PcieRpSlotImplemented[8]" = "1" end end end diff --git a/src/mainboard/system76/gaze16/variants/3060/overridetree.cb b/src/mainboard/system76/gaze16/variants/3060/overridetree.cb index 044df55457..7d5549935c 100644 --- a/src/mainboard/system76/gaze16/variants/3060/overridetree.cb +++ b/src/mainboard/system76/gaze16/variants/3060/overridetree.cb @@ -62,6 +62,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 10 (SSD2) @@ -69,6 +70,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" + register "PcieRpSlotImplemented[8]" = "1" end device ref gbe on end end diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 96ee0a1b9c..f097bacece 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -243,6 +243,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[2]" = "1" register "PcieClkSrcUsage[1]" = "2" register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[2]" = "1" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) @@ -258,6 +259,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[8]" = "1" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly) diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index e6372fd8ab..b85818d892 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -188,6 +188,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 6 (SSD2) @@ -195,6 +196,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[6]" = "8" register "PcieClkSrcClkReq[6]" = "6" + register "PcieRpSlotImplemented[8]" = "1" end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fb0d8278b8..59651d58b3 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -248,6 +248,8 @@ struct soc_intel_tigerlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* Implemented as slot or built-in? */ + uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index f04c3d7b5a..1cf3d2fee8 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -402,6 +402,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; params->PciePtm[i] = config->PciePtm[i]; + params->PcieRpSlotImplemented[i] = config->PcieRpSlotImplemented[i]; } /* Enable ClkReqDetect for enabled port */