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superio/ite/it8705f: Remove poor implementation 

This super io support is poorly implemented and would not work for all
boards since it hardcodes values. Since there are no users of it, remove
for now pending a fresh reimplementation from scratch.

Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5566
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Edward O'Callaghan 2014-04-23 04:00:38 +10:00 committed by Patrick Georgi
parent 5c41ee69ef
commit 45b7b5af76
6 changed files with 0 additions and 217 deletions
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2
src/superio/ite/Kconfig
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@ -24,8 +24,6 @@ config SUPERIO_ITE_IT8671F
bool
config SUPERIO_ITE_IT8673F
bool
config SUPERIO_ITE_IT8705F
bool
config SUPERIO_ITE_IT8712F
bool
config SUPERIO_ITE_IT8716F

1
src/superio/ite/Makefile.inc
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@ -20,7 +20,6 @@
subdirs-y += it8661f
subdirs-y += it8671f
subdirs-y += it8673f
subdirs-y += it8705f
subdirs-y += it8712f
subdirs-y += it8716f
subdirs-y += it8718f

22
src/superio/ite/it8705f/Makefile.inc
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@ -1,22 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ramstage-$(CONFIG_SUPERIO_ITE_IT8705F) += superio.c

82
src/superio/ite/it8705f/early_serial.c
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@ -1,82 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include "it8705f.h"
/* The base address is 0x2e or 0x4e, depending on config bytes. */
#define SIO_BASE 0x2e
#define SIO_INDEX SIO_BASE
#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */
#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */
#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */
#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */
#define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */
static void it8705f_sio_write(u8 ldn, u8 index, u8 value)
{
outb(IT8705F_CONFIG_REG_LDN, SIO_BASE);
outb(ldn, SIO_DATA);
outb(index, SIO_BASE);
outb(value, SIO_DATA);
}
/* Enable the serial port(s). */
static void it8705f_enable_serial(device_t dev, u16 iobase)
{
/* (1) Enter the configuration state (MB PnP mode). */
/* Perform MB PnP setup to put the SIO chip at 0x2e. */
/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
outb(0x87, IT8705F_CONFIGURATION_PORT);
outb(0x01, IT8705F_CONFIGURATION_PORT);
outb(0x55, IT8705F_CONFIGURATION_PORT);
outb(0x55, IT8705F_CONFIGURATION_PORT);
/* (2) Modify the data of configuration registers. */
/*
* Select the chip to configure (if there's more than one).
* Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
* If this register is not written, both chips are configured.
*/
/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */
/* Enable serial port(s). */
it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */
it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */
/* Select 24MHz CLKIN (set bit 0). */
it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01);
/* Clear software suspend mode (clear bit 0). TODO: Needed? */
/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */
/* (3) Exit the configuration state (MB PnP mode). */
it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);
}

38
src/superio/ite/it8705f/it8705f.h
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@ -1,38 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_ITE_IT8705F_IT8705F_H
#define SUPERIO_ITE_IT8705F_IT8705F_H
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8705_2.asp */
/* Note: This should also work on an IT8705AF, they're almost the same. */
#define IT8705F_FDC 0x00 /* Floppy */
#define IT8705F_SP1 0x01 /* Com1 */
#define IT8705F_SP2 0x02 /* Com2 */
#define IT8705F_PP 0x03 /* Parallel port */
#define IT8705F_EC 0x04 /* Environment controller */
#define IT8705F_GPIO 0x05 /* GPIO */
#define IT8705F_GAME 0x06 /* GAME port */
#define IT8705F_IR 0x07 /* Consumer IR */
#define IT8705F_MIDI 0x08 /* MIDI port */
#endif

72
src/superio/ite/it8705f/superio.c
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@ -1,72 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include <device/pnp.h>
#include <stdlib.h>
#include "it8705f.h"
static void init(device_t dev)
{
if (!dev->enabled)
return;
switch (dev->path.pnp.device) {
case IT8705F_FDC: /* TODO. */
break;
case IT8705F_PP: /* TODO. */
break;
case IT8705F_EC: /* TODO. */
break;
case IT8705F_GPIO: /* TODO. */
break;
case IT8705F_GAME: /* TODO. */
break;
case IT8705F_IR: /* TODO. */
break;
case IT8705F_MIDI: /* TODO. */
break;
}
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = pnp_set_resources,
.enable_resources = pnp_enable_resources,
.enable = pnp_enable,
.init = init,
};
/* TODO: FDC, PP, EC, GPIO, GAME, IR, MIDI. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_ite_it8705f_ops = {
CHIP_NAME("ITE IT8705F Super I/O")
.enable_dev = enable_dev,
};