src: Remove unused include <halt.h>

Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/apple/macbook21/romstage.c

@@ -26,7 +26,6 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-#include <halt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>

src/mainboard/asus/p5gc-mx/romstage.c

@@ -29,7 +29,6 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
-#include <halt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>

src/mainboard/asus/p5qpl-am/romstage.c

@@ -24,7 +24,6 @@
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
-#include <halt.h>
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <southbridge/intel/common/gpio.h>

src/mainboard/getac/p470/romstage.c

@@ -25,7 +25,6 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
-#include <halt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>

src/mainboard/ibase/mb899/romstage.c

@@ -16,7 +16,6 @@
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
 #include <stdint.h>
-#include <halt.h>
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/pnp_ops.h>

src/mainboard/intel/dcp847ske/early_southbridge.c

@@ -17,7 +17,6 @@
  */
 
 #include <stdint.h>
-#include <halt.h>
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/pci_ops.h>

src/mainboard/kontron/986lcd-m/romstage.c

@@ -16,7 +16,6 @@
 /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
 
 #include <stdint.h>
-#include <halt.h>
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <console/console.h>

src/mainboard/lenovo/t60/romstage.c

@@ -28,7 +28,6 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
-#include <halt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>

src/mainboard/lenovo/z61t/romstage.c

@@ -29,7 +29,6 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
-#include <halt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>

src/mainboard/roda/rk886ex/romstage.c

@@ -27,7 +27,6 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
-#include <halt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>

src/northbridge/intel/haswell/raminit.c

@@ -20,7 +20,6 @@
 #include <arch/cbfs.h>
 #include <cbfs.h>
 #include <cf9_reset.h>
-#include <halt.h>
 #include <ip_checksum.h>
 #include <memory_info.h>
 #include <mrc_cache.h>

src/northbridge/intel/i945/early_init.c

@@ -21,7 +21,6 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cbmem.h>
-#include <halt.h>
 #include <romstage_handoff.h>
 #include "i945.h"
 #include <pc80/mc146818rtc.h>

src/northbridge/intel/i945/raminit.c

@@ -26,7 +26,6 @@
 #include <pc80/mc146818rtc.h>
 #include <spd.h>
 #include <string.h>
-#include <halt.h>
 #include "raminit.h"
 #include "i945.h"
 #include "chip.h"

src/northbridge/intel/pineview/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <cf9_reset.h>
-#include <halt.h>
 #include <romstage_handoff.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>

src/northbridge/intel/sandybridge/raminit.c

@@ -25,7 +25,6 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
-#include <halt.h>
 #include <timestamp.h>
 #include <mrc_cache.h>
 #include <southbridge/intel/bd82x6x/me.h>

src/northbridge/intel/sandybridge/raminit_mrc.c

@@ -28,7 +28,6 @@
 #include <device/pci_def.h>
 #include <lib.h>
 #include <mrc_cache.h>
-#include <halt.h>
 #include <timestamp.h>
 #include "raminit.h"
 #include "pei_data.h"