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northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged 

Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11980
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
This commit is contained in:
Timothy Pearson 2015-06-08 19:54:56 -05:00 committed by Ronald G. Minnich
parent 83abd81c8a
commit 45de61de8b
3 changed files with 23 additions and 2 deletions
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3
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -1368,6 +1368,7 @@ restartinit:
printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n");
if (restore_mct_information_from_nvram(0) != 0)
printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__);
pMCTstat->GStatus |= 1 << GSB_ConfigRestored;
#endif
printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
@ -2095,6 +2096,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
if (is_fam15h())
exit_training_mode_fam15(pMCTstat, pDCTstatA);
pMCTstat->GStatus |= 1 << GSB_ConfigRestored;
}
/* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */

1
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
View File

@ -312,6 +312,7 @@ struct MCTStatStruc {
#define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/
#define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */
/* NOTE: This is a local bit used by memory code */
#define GSB_ConfigRestored 18 /* Training configuration was restored from NVRAM */
/*===============================================================================
Local DCT Status structure (a structure for each DCT)

21
src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
View File

@ -209,7 +209,7 @@ static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t d
return pci_read_config32(dev, reg);
}
static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data)
static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t * restored)
{
uint8_t node;
uint8_t dimm;
@ -232,6 +232,13 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data*
for (node = 0; node < MAX_NODES_SUPPORTED; node++)
for (channel = 0; channel < 2; channel++)
persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed;
if (restored) {
if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored))
*restored = 1;
else
*restored = 0;
}
}
void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data)
@ -1030,6 +1037,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
int8_t save_mct_information_to_nvram(void)
{
uint8_t nvram;
uint8_t restored = 0;
if (acpi_is_wakeup_s3())
return 0;
@ -1051,7 +1059,16 @@ int8_t save_mct_information_to_nvram(void)
copy_mct_data_to_save_variable(persistent_data);
/* Save RAM SPD data at the same time */
copy_cbmem_spd_data_to_save_variable(persistent_data);
copy_cbmem_spd_data_to_save_variable(persistent_data, &restored);
if (restored) {
/* Allow training bypass if DIMM configuration is unchanged on next boot */
nvram = 1;
set_option("allow_spd_nvram_cache_restore", &nvram);
printk(BIOS_DEBUG, "Hardware configuration unchanged since last boot; skipping write\n");
return 0;
}
/* Obtain CBFS file offset */
s3nv_offset = get_s3nv_file_offset();