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Add/Combine Broadwell Chromebooks using variant board scheme 

Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.

Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]

Additionally, some minor cleanup/changes were made:
 - I2C devices set to use level (vs edge) interrupt triggering
 - HDA verb entries use simplified macro entry format
 - correct FADT table header version
 - remove unused ACPI device entries / .asl file(s)
 - clean up ACPI code (e.g., trackpad on Lulu)
 - adjust _CID for trackpad on Lulu in order to not load non-functional
    Windows driver (does not affect Linux)
 - remove unused header includes (multiple/various)
 - correct I2C addresses used for SMBIOS device entries
 - correct misc typos etc

The existing auron_paine samus boards are removed.

Variant setup modeled after google/slippy

Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Matt DeVillier 2016-12-18 11:59:58 -06:00 committed by Martin Roth
parent 0148fcb4e1
commit 45e11aa0a5
144 changed files with 2701 additions and 3316 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
src/mainboard/google/auron/Kconfig
View File

@ -1,7 +1,6 @@
if BOARD_GOOGLE_AURON
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
config BOARD_GOOGLE_BASEBOARD_AURON
def_bool n
select SOC_INTEL_BROADWELL
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
@ -13,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
if BOARD_GOOGLE_BASEBOARD_AURON
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
select EC_GOOGLE_CHROMEEC_SWITCHES
@ -25,13 +26,46 @@ config MAINBOARD_DIR
string
default google/auron
config VARIANT_DIR
string
default "auron_paine" if BOARD_GOOGLE_AURON_PAINE
default "auron_yuna" if BOARD_GOOGLE_AURON_YUNA
default "gandof" if BOARD_GOOGLE_GANDOF
default "lulu" if BOARD_GOOGLE_LULU
default "samus" if BOARD_GOOGLE_SAMUS
config MAINBOARD_PART_NUMBER
string
default "Auron"
default "Auron_Paine" if BOARD_GOOGLE_AURON_PAINE
default "Auron_Yuna" if BOARD_GOOGLE_AURON_YUNA
default "Gandof" if BOARD_GOOGLE_GANDOF
default "Lulu" if BOARD_GOOGLE_LULU
default "Samus" if BOARD_GOOGLE_SAMUS
config IRQ_SLOT_COUNT
int
default 18
config GBB_HWID
string
depends on CHROMEOS
default "PAINE TEST A-A 8843" if BOARD_GOOGLE_AURON_PAINE
default "YUNA TEST A-A 3347" if BOARD_GOOGLE_AURON_YUNA
default "GANDOF TEST A-A 7705" if BOARD_GOOGLE_GANDOF
default "LULU TEST A-A 7705" if BOARD_GOOGLE_LULU
default "SAMUS TEST 8028" if BOARD_GOOGLE_SAMUS
config DEVICETREE
string
default "variants/auron_paine/devicetree.cb" if BOARD_GOOGLE_AURON_PAINE
default "variants/auron_yuna/devicetree.cb" if BOARD_GOOGLE_AURON_YUNA
default "variants/gandof/devicetree.cb" if BOARD_GOOGLE_GANDOF
default "variants/lulu/devicetree.cb" if BOARD_GOOGLE_LULU
default "variants/samus/devicetree.cb" if BOARD_GOOGLE_SAMUS
config EC_GOOGLE_CHROMEEC_BOARDNAME
string
default "auron" if BOARD_GOOGLE_AURON_PAINE
default "auron" if BOARD_GOOGLE_AURON_YUNA
default "" if BOARD_GOOGLE_GANDOF
default "" if BOARD_GOOGLE_LULU
default "samus" if BOARD_GOOGLE_SAMUS
config MAX_CPUS
int
@ -39,7 +73,7 @@ config MAX_CPUS
config VGA_BIOS_FILE
string
default "pci8086,0166.rom"
default "pci8086,0406.rom"
config HAVE_IFD_BIN
bool
@ -49,19 +83,4 @@ config HAVE_ME_BIN
bool
default n
config MAINBOARD_FAMILY
string
depends on GENERATE_SMBIOS_TABLES
default "Google_Auron"
config EC_GOOGLE_CHROMEEC_BOARDNAME
string
default "auron"
config GBB_HWID
string
depends on CHROMEOS
default "AURON TEST A-A 9944"
endif

21
src/mainboard/google/auron/Kconfig.name
View File

@ -1,2 +1,19 @@
config BOARD_GOOGLE_AURON
bool "Auron"
config BOARD_GOOGLE_AURON_PAINE
bool "Auron_Paine"
select BOARD_GOOGLE_BASEBOARD_AURON
config BOARD_GOOGLE_AURON_YUNA
bool "Auron_Yuna"
select BOARD_GOOGLE_BASEBOARD_AURON
config BOARD_GOOGLE_GANDOF
bool "Gandof"
select BOARD_GOOGLE_BASEBOARD_AURON
config BOARD_GOOGLE_LULU
bool "Lulu"
select BOARD_GOOGLE_BASEBOARD_AURON
config BOARD_GOOGLE_SAMUS
bool "Samus"
select BOARD_GOOGLE_BASEBOARD_AURON

19
src/mainboard/google/auron/Makefile.inc
View File

@ -13,15 +13,20 @@
## GNU General Public License for more details.
##
subdirs-y += spd
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += chromeos.c
ramstage-y += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += pei_data.c
ramstage-y += pei_data.c
romstage-y += variants/$(VARIANT_DIR)/pei_data.c
ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
romstage-y += variants/$(VARIANT_DIR)/variant.c
ramstage-y += variants/$(VARIANT_DIR)/variant.c
subdirs-y += variants/$(VARIANT_DIR)
subdirs-y += variants/$(VARIANT_DIR)/spd
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

82
src/mainboard/google/auron/acpi/haswell_pci_irqs.asl
View File

@ -1,82 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for IvyBridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// Mini-HD Audio 0:3.0
Package() { 0x0003ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 22 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 16 },
Package() { 0x001cffff, 1, 0, 17 },
Package() { 0x001cffff, 2, 0, 18 },
Package() { 0x001cffff, 3, 0, 19 },
// EHCI 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// XHCI 0:14.0
Package() { 0x0014ffff, 0, 0, 18 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 22 },
Package() { 0x001fffff, 1, 0, 18 },
Package() { 0x001fffff, 2, 0, 17 },
Package() { 0x001fffff, 3, 0, 16 },
// Serial IO 0:15.0
Package() { 0x0015ffff, 0, 0, 20 },
Package() { 0x0015ffff, 1, 0, 21 },
Package() { 0x0015ffff, 2, 0, 21 },
Package() { 0x0015ffff, 3, 0, 21 },
// SDIO 0:17.0
Package() { 0x0017ffff, 0, 0, 23 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// Mini-HD Audio 0:3.0
Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// XHCI 0:14.0
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
// Serial IO 0:15.0
Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
// SDIO 0:17.0
Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
})
}
}

243
src/mainboard/google/auron/acpi/mainboard.asl
View File

@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
#include <mainboard/google/auron/onboard.h>
#include <variant/onboard.h>
Scope (\_SB)
{
@ -27,7 +27,6 @@ Scope (\_SB)
Return (\LIDS)
}
// There is no GPIO for LID, the EC pulses WAKE# pin instead.
// There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
@ -43,255 +42,27 @@ Scope (\_SB)
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
Scope (\_SB.PCI0.I2C0)
{
Device (ETPA)
{
Name (_HID, "ELAN0000")
Name (_DDN, "Elan Touchpad")
Name (_UID, 1)
Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x15, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
})
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
Device (CTPA)
{
Name (_HID, "CYAP0000")
Name (_DDN, "Cypress Touchpad")
Name (_UID, 3)
Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x67, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
})
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
Device (CTPB)
{
Name (_HID, "CYAP0001")
Name (_DDN, "Cypress Touchpad")
Name (_UID, 3)
Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x24, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
})
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
}
Scope (\_SB.PCI0.I2C1)
{
Device (ATSA)
{
Name (_HID, "ATML0001")
Name (_DDN, "Atmel Touchscreen")
Name (_UID, 5)
Name (_S0W, 4)
Name (ISTP, 0) /* TouchScreen */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x4a, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C1", // ResourceSource
)
// GPIO54 (ball L3) is PIRQW: PIRQL_GSI + PIRQL - PIRQW = PIRQW_GSI
// 27 + 3 - 14 = 38
Interrupt (ResourceConsumer, Edge, ActiveLow) { 38 }
})
Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
Method (_STA)
{
If (LEqual (\S2EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
}
Device (ALSI)
{
/*
* TODO(dlaurie): Need official HID.
*
* The current HID is created from the Intersil PNP
* Vendor ID "LSD" and a shortened device identifier.
*/
Name (_HID, EisaId ("LSD2918"))
Name (_DDN, "Intersil 29018 Ambient Light Sensor")
Name (_UID, 6)
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x44, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.I2C1", // ResourceSource
)
// On Auron/Peppy board, IRQ is hooked to GPIO 51.
// Based on table 5-36, this is PIRQT. Then based on
// table 5-12, this is IRQ #35.
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
35
}
})
Method (_STA)
{
If (LEqual (\S2EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
}
}
Scope (\_SB.PCI0.RP01)
{
Device (WLAN)
{
Name (_ADR, 0x00000000)
/* GPIO10 is WLAN_WAKE_L_Q */
Name (GPIO, 10)
Name (_PRW, Package() { GPIO, 3 })
Name (_PRW, Package() { BOARD_WLAN_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_WLAN_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
}
}
#include <variant/acpi/mainboard.asl>

82
src/mainboard/google/auron/acpi/platform.asl
View File

@ -1,82 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
APMC, 8, // APM command
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (POST, SystemIO, 0x80, 1)
Field (POST, ByteAcc, Lock, Preserve)
{
DBG0, 8
}
/* SMI I/O Trap */
Method(TRAP, 1, Serialized)
{
Store (Arg0, SMIF) // SMI Function
Store (0, TRP0) // Generate trap
Return (SMIF) // Return value of SMI handler
}
/* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
Method(_PIC, 1)
{
// Remember the OS' IRQ routing choice.
Store(Arg0, PICM)
}
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method(_PTS,1)
{
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
/* Update AC status */
Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
if (LNotEqual (Local0, \PWRS)) {
Store (Local0, \PWRS)
Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
}
/* Update LID status */
Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
if (LNotEqual (Local0, \LIDS)) {
Store (Local0, \LIDS)
Notify (\_SB.LID0, 0x80)
}
Return(Package(){0,0})
}

2
src/mainboard/google/auron/acpi/thermal.asl
View File

@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
#include <mainboard/google/auron/thermal.h>
#include <variant/thermal.h>
// Thermal Zone

14
src/mainboard/google/auron/acpi_tables.c
View File

@ -13,27 +13,15 @@
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
#include "thermal.h"
extern const unsigned char AmlCode[];
#include <variant/thermal.h>
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->tmps = CTL_TDP_SENSOR_ID;
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tmax = MAX_TEMPERATURE;

4
src/mainboard/google/auron/ec.h
View File

@ -36,6 +36,7 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
#define MAINBOARD_EC_SMI_EVENTS \
@ -54,6 +55,7 @@
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
#endif

2
src/mainboard/google/auron/fadt.c
View File

@ -24,7 +24,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = 5;
header->revision = 3;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);

107
src/mainboard/google/auron/hda_verb.c
View File

@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
@ -13,107 +11,4 @@
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
0x10ec0283, // Subsystem ID
0x0000000d, // Number of jacks (NID entries)
0x0017ff00, // Function Reset
0x0017ff00, // Double Function Reset
0x000F0000, // Pad - get vendor id
0x000F0002, // Pad - get revision id
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
0x00172083,
0x00172102,
0x001722ec,
0x00172310,
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) DMIC - Disabled */
0x01271cf0, //
0x01271d11, //
0x01271e11, //
0x01271f41, //
/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
0x01471c10, // group 1, cap 0
0x01471d01, // no connector, no jack detect
0x01471e17, // speaker out, analog
0x01471f90, // fixed function, internal, Location N/A
/* Pin Complex (NID 0x17) MONO Out - Disabled */
0x01771cf0, //
0x01771d11, //
0x01771e11, //
0x01771f41, //
/* Pin Complex (NID 0x18) Disabled */
0x01871cf0, //
0x01871d11, //
0x01871e11, //
0x01871f41, //
/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
0x01971c20, // group2, cap 0
0x01971d10, // black, jack detect
0x01971ea1, // Mic in, 3.5mm Jack
0x01971f03, // connector, External left panel
/* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
0x01a71c11, // group 1, cap 1
0x01a71d01, // no connector, no jack detect
0x01a71ea7, // mic in, analog connection
0x01a71f90, // Fixed function, internal, Location N/A
/* Pin Complex (NID 0x1B) LINE2 - Disabled */
0x01b71cf0, //
0x01b71d11, //
0x01b71e11, //
0x01b71f41, //
/* Pin Complex (NID 0x1D) PCBeep */
0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
0x01d71d81, // mute spkr on hpout
0x01d71e15, // pcbeep en able, checksum
0x01d71f40, // no physical, Internal, Location N/A
/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
0x01e71cf0, //
0x01e71d11, //
0x01e71e11, //
0x01e71f41, //
/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
0x02171c21, // group2, cap 1
0x02171d10, // black, jack detect
0x02171e21, // HPOut, 3.5mm Jack
0x02171f03, // connector, left panel
/* Undocumented settings from Realtek (needed for beep_gen) */
/* Widget node 0x20 */
0x02050010,
0x02040c20,
0x0205001b,
0x0204081b,
};
const u32 pc_beep_verbs[] = {
0x00170500, /* power up everything (codec, dac, adc, mixers) */
0x01470740, /* enable speaker out */
0x01470c02, /* set speaker EAPD pin */
0x0143b01f, /* unmute speaker */
0x00c37100, /* unmute mixer nid 0xc input 1 */
0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
};
AZALIA_ARRAY_SIZES;
#include <variant/hda_verb.h>

55
src/mainboard/google/auron/mainboard.c
View File

@ -14,23 +14,10 @@
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <smbios.h>
#include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "onboard.h"
#include "variant.h"
static void mainboard_init(device_t dev)
@ -41,45 +28,7 @@ static void mainboard_init(device_t dev)
static int mainboard_smbios_data(device_t dev, int *handle,
unsigned long *current)
{
int len = 0;
len += smbios_write_type41(
current, handle,
BOARD_LIGHTSENSOR_NAME, /* name */
BOARD_LIGHTSENSOR_IRQ, /* instance */
BOARD_LIGHTSENSOR_I2C_BUS, /* segment */
BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
len += smbios_write_type41(
current, handle,
BOARD_TRACKPAD_NAME, /* name */
BOARD_TRACKPAD_IRQ, /* instance */
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
len += smbios_write_type41(
current, handle,
BOARD_TRACKPAD_NAME, /* name */
BOARD_TRACKPAD_IRQ, /* instance */
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_GEN5_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
len += smbios_write_type41(
current, handle,
BOARD_TOUCHSCREEN_NAME, /* name */
BOARD_TOUCHSCREEN_IRQ, /* instance */
BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
return len;
return variant_smbios_data(dev, handle, current);
}
// mainboard_enable is executed as first thing after

9
src/mainboard/google/auron/romstage.c
View File

@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
#include <cbfs.h>
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
@ -22,8 +21,9 @@
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
#include <mainboard/google/auron/spd/spd.h>
#include "gpio.h"
#include <variant/gpio.h>
#include <variant/spd.h>
#include "variant.h"
void mainboard_romstage_entry(struct romstage_params *rp)
{
@ -45,4 +45,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
/* Do variant-specific (read: Samus) init */
variant_romstage_entry(rp);
}

29
src/mainboard/google/auron/smihandler.c
View File

@ -25,15 +25,8 @@
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/nvs.h>
#include <soc/pm.h>
#include <soc/smm.h>
#include "ec.h"
/* Codec enable: GPIO45 */
#define GPIO_PP3300_CODEC_EN 45
/* WLAN / BT enable: GPIO46 */
#define GPIO_WLAN_DISABLE_L 46
#include <variant/onboard.h>
static u8 mainboard_smi_ec(void)
{
@ -70,6 +63,20 @@ void mainboard_smi_gpi(u32 gpi_sts)
}
}
static void mainboard_disable_gpios(void)
{
#if IS_ENABLED(CONFIG_BOARD_GOOGLE_SAMUS)
/* Put SSD in reset to prevent leak */
set_gpio(BOARD_SSD_RESET_GPIO, 0);
/* Disable LTE */
set_gpio(BOARD_LTE_DISABLE_GPIO, 0);
#else
set_gpio(BOARD_PP3300_CODEC_GPIO, 0);
#endif
/* Prevent leak from standby rail to WLAN rail */
set_gpio(BOARD_WLAN_DISABLE_GPIO, 0);
}
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
@ -82,8 +89,7 @@ void mainboard_smi_sleep(u8 slp_typ)
1, USB_CHARGE_MODE_DISABLED);
}
set_gpio(GPIO_PP3300_CODEC_EN, 0);
set_gpio(GPIO_WLAN_DISABLE_L, 0);
mainboard_disable_gpios();
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
@ -96,8 +102,7 @@ void mainboard_smi_sleep(u8 slp_typ)
1, USB_CHARGE_MODE_DISABLED);
}
set_gpio(GPIO_PP3300_CODEC_EN, 0);
set_gpio(GPIO_WLAN_DISABLE_L, 0);
mainboard_disable_gpios();
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);

15
src/mainboard/google/auron_paine/acpi/ec.asl → src/mainboard/google/auron/variant.h
View File

@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@ -13,8 +11,13 @@
* GNU General Public License for more details.
*/
/* mainboard configuration */
#include <mainboard/google/auron_paine/ec.h>
#ifndef VARIANT_H
#define VARIANT_H
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
#include <arch/io.h>
#include <soc/romstage.h>
int variant_smbios_data(device_t dev, int *handle, unsigned long *current);
void variant_romstage_entry(struct romstage_params *rp);
#endif

0
src/mainboard/google/auron_paine/devicetree.cb → src/mainboard/google/auron/variants/auron_paine/devicetree.cb
View File

66
src/mainboard/google/auron_paine/acpi/mainboard.asl → src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl
View File

@ -14,39 +14,6 @@
* GNU General Public License for more details.
*/
#include <mainboard/google/auron_paine/onboard.h>
Scope (\_SB)
{
Device (LID0)
{
Name(_HID, EisaId("PNP0C0D"))
Method(_LID, 0)
{
Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
Return (\LIDS)
}
// There is no GPIO for LID, the EC pulses WAKE# pin instead.
// There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
}
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
}
/*
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
Scope (\_SB.PCI0.I2C0)
{
Device (ETPA)
@ -59,13 +26,13 @@ Scope (\_SB.PCI0.I2C0)
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x15, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Edge, ActiveLow)
Interrupt (ResourceConsumer, Level, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
@ -95,24 +62,3 @@ Scope (\_SB.PCI0.I2C0)
Name (_S0W, 4)
}
}
Scope (\_SB.PCI0.RP01)
{
Device (WLAN)
{
Name (_ADR, 0x00000000)
/* GPIO10 is WLAN_WAKE_L_Q */
Name (GPIO, 10)
Name (_PRW, Package() { GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
}
}
}
}

4
src/mainboard/google/auron_paine/gpio.h → src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h
View File

@ -25,8 +25,8 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 3: UNUSED */
PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
PCH_GPIO_UNUSED, /* 6: UNUSED */
PCH_GPIO_UNUSED, /* 7: UNUSED */
PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
PCH_GPIO_INPUT, /* 9: RAM_ID1 */
PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */

112
src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h Normal file
View File

@ -0,0 +1,112 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
0x10ec0283, // Subsystem ID
0x0000000e, // Number of jacks (NID entries)
0x0017ff00, // Function Reset
0x0017ff00, // Double Function Reset
0x000F0000, // Pad - get vendor id
0x000F0002, // Pad - get revision id
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
AZALIA_SUBVENDOR(0x0, 0x11790670),
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) DMIC - Disabled */
AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
// group 1, cap 0
// no connector, no jack detect
// speaker out, analog
// fixed function, internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
/* Pin Complex (NID 0x17) MONO Out - Disabled */
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
/* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */
AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
// group2, cap 0
// black, jack detect
// Mic in, 3.5mm Jack
// connector, External left panel
AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
/* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
// group 1, cap 1
// no connector, no jack detect
// mic in, analog connection
// Fixed function, internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x1A, 0x90a70111),
/* Pin Complex (NID 0x1B) LINE2 - Disabled */
AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
/* Pin Complex (NID 0x1D) PCBeep */
// eapd low on ex-amp, laptop, custom enable
// mute spkr on hpout
// pcbeep en able, checksum
// no physical, Internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d),
/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
// group2, cap 1
// black, jack detect
// HPOut, 3.5mm Jack
// connector, left panel
AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
/* Undocumented settings from Realtek (needed for beep_gen) */
/* Widget node 0x20 */
0x02050010,
0x02040c20,
0x0205001b,
0x0204081b,
/* Tuned jack detection */
0x02050043,
0x0204A614,
0x02050047,
0x02049470,
};
const u32 pc_beep_verbs[] = {
0x00170500, /* power up everything (codec, dac, adc, mixers) */
0x01470740, /* enable speaker out */
0x01470c02, /* set speaker EAPD pin */
0x0143b01f, /* unmute speaker */
0x00c37100, /* unmute mixer nid 0xc input 1 */
0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
};
AZALIA_ARRAY_SIZES;

7
src/mainboard/google/auron_paine/onboard.h → src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h
View File

@ -20,7 +20,10 @@
#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
#define BOARD_TRACKPAD_I2C_ADDR 0x67
#define BOARD_TRACKPAD_GEN5_I2C_ADDR 0x24
#define BOARD_TRACKPAD_I2C_ADDR 0x15
#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */
#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */
#endif

6
src/mainboard/google/auron/spd/spd.h → src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h
View File

@ -19,14 +19,14 @@
#define SPD_LEN 256
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
#define SPD_PART_LEN 18
/* Auron board memory configuration GPIOs */
#define SPD_GPIO_BIT0 13

0
src/mainboard/google/auron/thermal.h → src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h
View File

0
src/mainboard/google/auron/pei_data.c → src/mainboard/google/auron/variants/auron_paine/pei_data.c
View File

0
src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex → src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex
View File

17
src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex Normal file
View File

@ -0,0 +1,17 @@
# Hynix HMT425S6CFR6A-PBA
92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

50
src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc Normal file
View File

@ -0,0 +1,50 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# { GPIO47, GPIO9, GPIO13 }
SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0010
SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0110
SPD_SOURCES += empty # 0b0111
SPD_SOURCES += empty # 0b1000
SPD_SOURCES += empty # 0b1001
SPD_SOURCES += empty # 0b1010
SPD_SOURCES += empty # 0b1011
SPD_SOURCES += empty # 0b1100
SPD_SOURCES += empty # 0b1101
SPD_SOURCES += empty # 0b1110
SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
do printf $$(printf '\%o' 0x$$c); \
done; \
done > $@
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := spd

0
src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex → src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.hex
View File

0
src/mainboard/google/auron/spd/empty.spd.hex → src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.hex
View File

4
src/mainboard/google/auron/spd/spd.c → src/mainboard/google/auron/variants/auron_paine/spd/spd.c
View File

@ -22,8 +22,8 @@
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron/ec.h>
#include <mainboard/google/auron/gpio.h>
#include <mainboard/google/auron/spd/spd.h>
#include <variant/gpio.h>
#include <variant/spd.h>
static void mainboard_print_spd_info(uint8_t spd[])
{

39
src/mainboard/google/auron/variants/auron_paine/variant.c Normal file
View File

@ -0,0 +1,39 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <smbios.h>
#include <soc/romstage.h>
#include <variant/onboard.h>
#include <mainboard/google/auron/variant.h>
int variant_smbios_data(device_t dev, int *handle,
unsigned long *current)
{
int len = 0;
len += smbios_write_type41(
current, handle,
BOARD_TRACKPAD_NAME, /* name */
BOARD_TRACKPAD_IRQ, /* instance */
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
return len;
}
void variant_romstage_entry(struct romstage_params *rp)
{
/* N/A for boards other than SAMUS */
}

2
src/mainboard/google/auron/devicetree.cb → src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
View File

@ -46,7 +46,7 @@ chip soc/intel/broadwell
register "sio_acpi_mode" = "1"
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port0_gen3_dtle" = "0x7"
register "sata_port1_gen3_dtle" = "0x5"
# Force enable ASPM for PCIe Port1

64
src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl Normal file
View File

@ -0,0 +1,64 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope (\_SB.PCI0.I2C0)
{
Device (ETPA)
{
Name (_HID, "ELAN0000")
Name (_DDN, "Elan Touchpad")
Name (_UID, 1)
Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Level, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
})
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
}

4
src/mainboard/google/auron/gpio.h → src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h
View File

@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
#ifndef AURON_GPIO_H
#define AURON_GPIO_H
#ifndef AURON_YUNA_GPIO_H
#define AURON_YUNA_GPIO_H
#include <soc/gpio.h>

112
src/mainboard/google/auron_paine/hda_verb.c → src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h
View File

@ -19,7 +19,7 @@ const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
0x10ec0283, // Subsystem ID
0x0000000d, // Number of jacks (NID entries)
0x00000013, // Number of jacks (NID entries)
0x0017ff00, // Function Reset
0x0017ff00, // Double Function Reset
@ -31,80 +31,94 @@ const u32 cim_verb_data[] = {
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
0x00172083,
0x00172102,
0x001722ec,
0x00172310,
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
AZALIA_SUBVENDOR(0x0, 0x11790670),
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) DMIC - Disabled */
0x01271cf0, //
0x01271d11, //
0x01271e11, //
0x01271f41, //
/* Pin Complex (NID 0x12) DMIC - Enabled */
AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130),
/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
0x01471c10, // group 1, cap 0
0x01471d01, // no connector, no jack detect
0x01471e17, // speaker out, analog
0x01471f90, // fixed function, internal, Location N/A
// group 1, cap 0
// no connector, no jack detect
// speaker out, analog
// fixed function, internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
/* Pin Complex (NID 0x17) MONO Out - Disabled */
0x01771cf0, //
0x01771d11, //
0x01771e11, //
0x01771f41, //
/* Pin Complex (NID 0x17) MONO Out - Enabled */
AZALIA_PIN_CFG(0x0, 0x17, 0x40000008),
/* Pin Complex (NID 0x18) Disabled */
0x01871cf0, //
0x01871d11, //
0x01871e11, //
0x01871f41, //
AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
0x01971c20, // group2, cap 0
0x01971d10, // black, jack detect
0x01971ea1, // Mic in, 3.5mm Jack
0x01971f03, // connector, External left panel
// group2, cap 0
// black, jack detect
// Mic in, 3.5mm Jack
// connector, External left panel
AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
/* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
0x01a71c11, // group 1, cap 1
0x01a71d01, // no connector, no jack detect
0x01a71ea7, // mic in, analog connection
0x01a71f90, // Fixed function, internal, Location N/A
/* Pin Complex (NID 0x1A) LINE1 - Disabled */
AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
/* Pin Complex (NID 0x1B) LINE2 - Disabled */
0x01b71cf0, //
0x01b71d11, //
0x01b71e11, //
0x01b71f41, //
AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
/* Pin Complex (NID 0x1D) PCBeep */
0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
0x01d71d81, // mute spkr on hpout
0x01d71e15, // pcbeep en able, checksum
0x01d71f40, // no physical, Internal, Location N/A
// eapd low on ex-amp, laptop, custom enable
// mute spkr on hpout
// pcbeep en able, checksum
// no physical, Internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d),
/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
0x01e71cf0, //
0x01e71d11, //
0x01e71e11, //
0x01e71f41, //
AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
0x02171c21, // group2, cap 1
0x02171d10, // black, jack detect
0x02171e21, // HPOut, 3.5mm Jack
0x02171f03, // connector, left panel
// group1
// black, jack detect
// HPOut, 3.5mm Jack
// connector, left panel
AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f),
/* Undocumented settings from Realtek (needed for beep_gen) */
/* Widget node 0x20 */
0x02050038,
0x02046900,
0x02050010,
0x02040C20,
/* Widget node 0x20 - 1 */
0x02050019,
0x02041857,
0x0205001A,
0x02044001,
/* Widget node 0x20 - 2 */
0x0205001B,
0x0204140B,
0x02050025,
0x0204802A,
/* Widget node 0x20 - 3 */
0x02050045,
0x02045029,
0x02050046,
0x02040004,
/* Widget node 0x20 - 4 */
0x02050043,
0x0204A614,
0x02050043,
0x0204A614,
/* pc beep */
0x02050010,
0x02040c20,
0x0205001b,
0x0204081b,
/* Tuned jack detection */
0x02050043,
0x0204A614,
0x02050047,
0x02049470,
};
const u32 pc_beep_verbs[] = {

20
src/mainboard/google/auron_paine/acpi/superio.asl → src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h
View File

@ -13,13 +13,17 @@
* GNU General Public License for more details.
*/
/* mainboard configuration */
#include <mainboard/google/auron_paine/ec.h>
#ifndef ONBOARD_H
#define ONBOARD_H
#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
#define BOARD_TRACKPAD_NAME "trackpad"
#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
#define BOARD_TRACKPAD_I2C_ADDR 0x15
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */
#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */
#endif

8
src/mainboard/google/auron_paine/spd/spd.h → src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h
View File

@ -19,16 +19,16 @@
#define SPD_LEN 256
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
#define SPD_PART_LEN 18
/* Auron_paine board memory configuration GPIOs */
/* Auron board memory configuration GPIOs */
#define SPD_GPIO_BIT0 13
#define SPD_GPIO_BIT1 9
#define SPD_GPIO_BIT2 47

0
src/mainboard/google/auron_paine/thermal.h → src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h
View File

0
src/mainboard/google/auron_paine/pei_data.c → src/mainboard/google/auron/variants/auron_yuna/pei_data.c
View File

16
src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex → src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex
View File

@ -1,14 +1,14 @@
# Elpida EDJ4216EFBG-GN-F
92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81
# Hynix HMT425S6AFR6A-PBA
92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE
45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46
00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

17
src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex Normal file
View File

@ -0,0 +1,17 @@
# Hynix HMT425S6CFR6A-PBA
92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

50
src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc Normal file
View File

@ -0,0 +1,50 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# { GPIO47, GPIO9, GPIO13 }
SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0010
SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0110
SPD_SOURCES += empty # 0b0111
SPD_SOURCES += empty # 0b1000
SPD_SOURCES += empty # 0b1001
SPD_SOURCES += empty # 0b1010
SPD_SOURCES += empty # 0b1011
SPD_SOURCES += empty # 0b1100
SPD_SOURCES += empty # 0b1101
SPD_SOURCES += empty # 0b1110
SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
do printf $$(printf '\%o' 0x$$c); \
done; \
done > $@
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := spd

17
src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.hex Normal file
View File

@ -0,0 +1,17 @@
# Micron 4KTF25664HZ-1G6E1
92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

0
src/mainboard/google/samus/spd/empty.spd.hex → src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.hex
View File

6
src/mainboard/google/auron_paine/spd/spd.c → src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
View File

@ -21,9 +21,9 @@
#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron_paine/ec.h>
#include <mainboard/google/auron_paine/gpio.h>
#include <mainboard/google/auron_paine/spd/spd.h>
#include <mainboard/google/auron/ec.h>
#include <variant/gpio.h>
#include <variant/spd.h>
static void mainboard_print_spd_info(uint8_t spd[])
{

39
src/mainboard/google/auron/variants/auron_yuna/variant.c Normal file
View File

@ -0,0 +1,39 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <smbios.h>
#include <soc/romstage.h>
#include <variant/onboard.h>
#include <mainboard/google/auron/variant.h>
int variant_smbios_data(device_t dev, int *handle,
unsigned long *current)
{
int len = 0;
len += smbios_write_type41(
current, handle,
BOARD_TRACKPAD_NAME, /* name */
BOARD_TRACKPAD_IRQ, /* instance */
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
return len;
}
void variant_romstage_entry(struct romstage_params *rp)
{
/* N/A for boards other than SAMUS */
}

108
src/mainboard/google/auron/variants/gandof/devicetree.cb Normal file
View File

@ -0,0 +1,108 @@
chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Disable DisplayPort C Hotplug
register "gpu_dp_c_hotplug" = "0x00"
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms
register "gpu_panel_power_backlight_on_delay" = "500" # 50ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8b"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
# EC_SMI is GPIO34
register "alt_gp_smi_en" = "0x0004"
register "gpe0_en_1" = "0x00000000"
# EC_SCI is GPIO36
register "gpe0_en_2" = "0x00000010"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1"
register "sio_acpi_mode" = "1"
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
# Force enable ASPM for PCIe Port1
register "pcie_port_force_aspm" = "0x01"
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
register "s0ix_enable" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA
device pci 15.1 on end # I2C0
device pci 15.2 on end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus
device pci 1f.6 on end # Thermal
end
end

64
src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl Normal file
View File

@ -0,0 +1,64 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope (\_SB.PCI0.I2C0)
{
Device (ETPA)
{
Name (_HID, "ELAN0000")
Name (_DDN, "Elan Touchpad")
Name (_UID, 1)
Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Level, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
})
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
}

120
src/mainboard/google/auron/variants/gandof/include/variant/gpio.h Normal file
View File

@ -0,0 +1,120 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef GANDOF_GPIO_H
#define GANDOF_GPIO_H
#include <soc/gpio.h>
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
PCH_GPIO_UNUSED, /* 3: UNUSED */
PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
PCH_GPIO_UNUSED, /* 8: UNUSED */
PCH_GPIO_INPUT, /* 9: RAM_ID1 */
PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
PCH_GPIO_UNUSED, /* 11: UNUSED */
PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
PCH_GPIO_INPUT, /* 13: RAM_ID0 */
PCH_GPIO_INPUT, /* 14: EC_IN_RW */
PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
PCH_GPIO_UNUSED, /* 16: UNUSED */
PCH_GPIO_UNUSED, /* 17: UNUSED */
PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
PCH_GPIO_UNUSED, /* 19: UNUSED */
PCH_GPIO_UNUSED, /* 20: UNUSED */
PCH_GPIO_UNUSED, /* 21: UNUSED */
PCH_GPIO_UNUSED, /* 22: UNUSED */
PCH_GPIO_UNUSED, /* 23: UNUSED */
PCH_GPIO_UNUSED, /* 24: UNUSED */
PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
PCH_GPIO_UNUSED, /* 26: UNUSED */
PCH_GPIO_UNUSED, /* 27: UNUSED */
PCH_GPIO_UNUSED, /* 28: UNUSED */
PCH_GPIO_UNUSED, /* 29: UNUSED */
PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
PCH_GPIO_UNUSED, /* 37: UNUSED */
PCH_GPIO_UNUSED, /* 38: UNUSED */
PCH_GPIO_UNUSED, /* 39: UNUSED */
PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
PCH_GPIO_UNUSED, /* 41: UNUSED */
PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
PCH_GPIO_UNUSED, /* 43: UNUSED */
PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
PCH_GPIO_INPUT, /* 47: RAM_ID2 */
PCH_GPIO_UNUSED, /* 48: UNUSED */
PCH_GPIO_UNUSED, /* 49: UNUSED */
PCH_GPIO_UNUSED, /* 50: UNUSED */
PCH_GPIO_UNUSED, /* 51: UNUSED */
PCH_GPIO_UNUSED, /* 52: UNUSED */
PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
PCH_GPIO_UNUSED, /* 55: UNUSED */
PCH_GPIO_UNUSED, /* 56: UNUSED */
PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
PCH_GPIO_UNUSED, /* 59: UNUSED */
PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
PCH_GPIO_UNUSED, /* 61: UNUSED */
PCH_GPIO_UNUSED, /* 62: UNUSED */
PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
PCH_GPIO_UNUSED, /* 64: UNUSED */
PCH_GPIO_UNUSED, /* 65: UNUSED */
PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
PCH_GPIO_UNUSED, /* 67: UNUSED */
PCH_GPIO_UNUSED, /* 68: UNUSED */
PCH_GPIO_UNUSED, /* 69: UNUSED */
PCH_GPIO_UNUSED, /* 70: UNUSED */
PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
PCH_GPIO_UNUSED, /* 76: UNUSED */
PCH_GPIO_UNUSED, /* 77: UNUSED */
PCH_GPIO_UNUSED, /* 78: UNUSED */
PCH_GPIO_UNUSED, /* 79: UNUSED */
PCH_GPIO_UNUSED, /* 80: UNUSED */
PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
PCH_GPIO_UNUSED, /* 83: UNUSED */
PCH_GPIO_UNUSED, /* 84: UNUSED */
PCH_GPIO_UNUSED, /* 85: UNUSED */
PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
PCH_GPIO_UNUSED, /* 87: UNUSED */
PCH_GPIO_UNUSED, /* 88: UNUSED */
PCH_GPIO_UNUSED, /* 89: UNUSED */
PCH_GPIO_UNUSED, /* 90: UNUSED */
PCH_GPIO_UNUSED, /* 91: UNUSED */
PCH_GPIO_UNUSED, /* 92: UNUSED */
PCH_GPIO_UNUSED, /* 93: UNUSED */
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};
#endif

112
src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h Normal file
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@ -0,0 +1,112 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
0x10ec0283, // Subsystem ID
0x0000000e, // Number of jacks (NID entries)
0x0017ff00, // Function Reset
0x0017ff00, // Double Function Reset
0x000F0000, // Pad - get vendor id
0x000F0002, // Pad - get revision id
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
AZALIA_SUBVENDOR(0x0, 0x11790670),
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) DMIC - Internal MIC */
// group 3, cap 0
// no connector, no jack detect
// mic in, digital
// fixed function, internal
AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130),
/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
// group 1, cap 0
// no connector, no jack detect
// speaker out, analog
// fixed function, internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
/* Pin Complex (NID 0x17) MONO Out - Disabled */
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
/* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */
AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
// group2, cap 0
// black, jack detect
// Mic in, 3.5mm Jack
// connector, External left panel
AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
/* Pin Complex (NID 0x1A) LINE1 - Disabled */
AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
/* Pin Complex (NID 0x1B) LINE2 - Disabled */
AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
/* Pin Complex (NID 0x1D) PCBeep */
// eapd low on ex-amp, laptop, custom enable
// mute spkr on hpout
// pcbeep en able, checksum
// no physical, Internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d),
/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */
AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack */
// group2, cap 1
// black, jack detect
// HPOut, 3.5mm Jack
// connector, left panel
AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
/* Undocumented settings from Realtek (needed for beep_gen) */
/* Widget node 0x20 */
0x02050010,
0x02040c20,
0x0205001b,
0x0204081b,
/* Tuned jack detection */
0x02050043,
0x0204A614,
0x02050047,
0x02049470,
};
const u32 pc_beep_verbs[] = {
0x00170500, /* power up everything (codec, dac, adc, mixers) */
0x01470740, /* enable speaker out */
0x01470c02, /* set speaker EAPD pin */
0x0143b01f, /* unmute speaker */
0x00c37100, /* unmute mixer nid 0xc input 1 */
0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
};
AZALIA_ARRAY_SIZES;

29
src/mainboard/google/auron/variants/gandof/include/variant/onboard.h Normal file
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@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef ONBOARD_H
#define ONBOARD_H
#define BOARD_TRACKPAD_NAME "trackpad"
#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
#define BOARD_TRACKPAD_I2C_ADDR 0x15
#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */
#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */
#endif

39
src/mainboard/google/auron/variants/gandof/include/variant/spd.h Normal file
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@ -0,0 +1,39 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#define SPD_LEN 256
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
/* Gandof board memory configuration GPIOs */
#define SPD_GPIO_BIT0 13
#define SPD_GPIO_BIT1 9
#define SPD_GPIO_BIT2 47
struct pei_data;
void mainboard_fill_spd_data(struct pei_data *pei_data);
#endif

35
src/mainboard/google/auron/variants/gandof/include/variant/thermal.h Normal file
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@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef THERMAL_H
#define THERMAL_H
/* Control TDP Settings */
#define CTL_TDP_SENSOR_ID 0 /* PECI */
#define CTL_TDP_POWER_LIMIT 9 /* 8W */
#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
#define CTL_TDP_THRESHOLD_OFF 66 /* Normal at 64C */
#define CTL_TDP_THRESHOLD_ON 75 /* Limited at 76C */
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 104
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 95
/* Tj_max value for calculating PECI CPU temperature */
#define MAX_TEMPERATURE 105
#endif

63
src/mainboard/google/auron/variants/gandof/pei_data.c Normal file
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@ -0,0 +1,63 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <string.h>
#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
/* One installed DIMM per channel -- can be changed by SPD init */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
USB_PORT_BACK_PANEL);
/* P2: CCD */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
/* P3: BT */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
/* P4: Port B, CN6 */
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
USB_PORT_BACK_PANEL);
/* P5: EMPTY */
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P6: SD Card */
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_FLEX);
/* P7: EMPTY */
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P1: Port A, CN6 */
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
/* P2: EMPTY */
pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
/* P3: EMPTY */
pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
/* P4: EMPTY */
pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
}

17
src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.hex Normal file
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@ -0,0 +1,17 @@
# Hynix HMT425S6AFR6A-PBA
92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

17
src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex Normal file
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@ -0,0 +1,17 @@
# Hynix HMT425S6CFR6A-PBA
92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

26
src/mainboard/google/auron/spd/Makefile.inc → src/mainboard/google/auron/variants/gandof/spd/Makefile.inc
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@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
## Copyright (C) 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@ -18,25 +18,25 @@ romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# { GPIO47, GPIO9, GPIO13 }
SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0010
SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0110
SPD_SOURCES += empty # 0b0111
SPD_SOURCES = Samsung_M471B5674EB0-YK0 # 0b0000
SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0001
SPD_SOURCES += empty # 0b0010
SPD_SOURCES += empty # 0b0011
SPD_SOURCES += Samsung_M471B5674EB0-YK0 # 0b0100
SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0101
SPD_SOURCES += empty # 0b0110
SPD_SOURCES += empty # 0b0111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
# Include spd ROM data
# Include spd rom data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
do echo -e -n "\\x$$c"; \
do printf $$(printf '\%o' 0x$$c); \
done; \
done > $@
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := spd
spd.bin-type := spd

17
src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.hex Normal file
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@ -0,0 +1,17 @@
# Micron 4KTF25664HZ-1G6E1
92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

17
src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex Normal file
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@ -0,0 +1,17 @@
# Samsung_M471B5674EB0-YK0
92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F
4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30
20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

16
src/mainboard/google/auron/variants/gandof/spd/empty.spd.hex Normal file
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@ -0,0 +1,16 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

132
src/mainboard/google/auron/variants/gandof/spd/spd.c Normal file
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@ -0,0 +1,132 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbfs.h>
#include <console/console.h>
#include <endian.h>
#include <string.h>
#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron/ec.h>
#include <variant/gpio.h>
#include <variant/spd.h>
static void mainboard_print_spd_info(uint8_t spd[])
{
const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
char spd_name[SPD_PART_LEN+1] = { 0 };
int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
/* Module type */
printk(BIOS_INFO, "SPD: module type is ");
switch (spd[SPD_DRAM_TYPE]) {
case SPD_DRAM_DDR3:
printk(BIOS_INFO, "DDR3\n");
break;
case SPD_DRAM_LPDDR3:
printk(BIOS_INFO, "LPDDR3\n");
break;
default:
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
break;
}
/* Module Part Number */
memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
spd_name[SPD_PART_LEN] = 0;
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
, banks, ranks, rows, cols);
printk(BIOS_INFO, "density %d Mb\n", capmb);
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
devw, busw);
if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
capmb / 8 * busw / devw * ranks);
}
}
/* Copy SPD data for on-board memory */
void mainboard_fill_spd_data(struct pei_data *pei_data)
{
int spd_bits[3] = {
SPD_GPIO_BIT0,
SPD_GPIO_BIT1,
SPD_GPIO_BIT2
};
int spd_gpio[3];
int spd_index;
size_t spd_file_len;
char *spd_file;
spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
spd_index,
spd_bits[2], spd_gpio[2],
spd_bits[1], spd_gpio[1],
spd_bits[0], spd_gpio[0]);
spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
if (!spd_file)
die("SPD data not found.");
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spd_index = 0;
}
if (spd_file_len < SPD_LEN)
die("Missing SPD data.");
memcpy(pei_data->spd_data[0][0],
spd_file + (spd_index * SPD_LEN), SPD_LEN);
/* Index 0-2 are 4GB config with both CH0 and CH1.
* Index 4-6 are 2GB config with CH0 only. */
if (spd_index > 3)
pei_data->dimm_channel1_disabled = 3;
else
memcpy(pei_data->spd_data[1][0],
spd_file + (spd_index * SPD_LEN), SPD_LEN);
/* Make sure a valid SPD was found */
if (pei_data->spd_data[0][0][0] == 0)
die("Invalid SPD data.");
mainboard_print_spd_info(pei_data->spd_data[0][0]);
}

39
src/mainboard/google/auron/variants/gandof/variant.c Normal file
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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <smbios.h>
#include <soc/romstage.h>
#include <variant/onboard.h>
#include <mainboard/google/auron/variant.h>
int variant_smbios_data(device_t dev, int *handle,
unsigned long *current)
{
int len = 0;
len += smbios_write_type41(
current, handle,
BOARD_TRACKPAD_NAME, /* name */
BOARD_TRACKPAD_IRQ, /* instance */
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
return len;
}
void variant_romstage_entry(struct romstage_params *rp)
{
/* N/A for boards other than SAMUS */
}

110
src/mainboard/google/auron/variants/lulu/devicetree.cb Normal file
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chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Disable DisplayPort C Hotplug
register "gpu_dp_c_hotplug" = "0x00"
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8b"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
# EC_SMI is GPIO34
register "alt_gp_smi_en" = "0x0004"
register "gpe0_en_1" = "0x00000000"
# EC_SCI is GPIO36
register "gpe0_en_2" = "0x00000010"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1"
register "sata_devslp_disable" = "1"
register "sio_acpi_mode" = "1"
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
# Force enable ASPM for PCIe Port1
register "pcie_port_force_aspm" = "0x01"
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
register "s0ix_enable" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA
device pci 15.1 on end # I2C0
device pci 15.2 on end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus
device pci 1f.6 on end # Thermal
end
end

138
src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope (\_SB.PCI0.I2C0)
{
Device (STPA)
{
Name (_HID, "SYNA0000")
Name (_CID, "ACPI0C50")
Name (_DDN, "Synaptics Touchpad")
Name (_UID, 1)
Name (ISTP, 1) /* Touchpad */
Method(_CRS, 0x0, Serialized)
{
Name (RBUF, ResourceTemplate()
{
I2cSerialBus (
BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Level, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
})
Return(RBUF)
}
Method(_DSM, 0x4, NotSerialized)
{
If (LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) /* I2C-HID UUID */
{
If (LEqual(Arg2, Zero)) /* DSM Function */
{
/* Function 0: Query function, return based on revision */
If (LEqual(Arg1, One)) /* Arg1 DSM Revision */
{
/* Revision 1: Function 0 supported */
Return(Buffer(One) { 0x03 })
}
} ElseIf (LEqual(Arg2, One)) /* Function 1 : HID Function */
{
Return(0x0020) /* HID Descriptor Address */
}
}
Return(Buffer(One) { 0x00 }) /* Not supported */
}
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
}
Scope (\_SB.PCI0.I2C1)
{
Device (ETSA)
{
Name (_HID, "ELAN0001")
Name (_DDN, "Elan Touchscreen")
Name (_UID, 6)
Name (ISTP, 0) /* Touchscreen */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C1", // ResourceSource
)
Interrupt (ResourceConsumer, Level, ActiveLow)
{
BOARD_TOUCHSCREEN_IRQ
}
})
Method (_STA)
{
If (LEqual (\S2EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
}

121
src/mainboard/google/auron/variants/lulu/include/variant/gpio.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Sage Electronic Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef LULU_GPIO_H
#define LULU_GPIO_H
#include <soc/gpio.h>
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
PCH_GPIO_UNUSED, /* 3: UNUSED */
PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
PCH_GPIO_INPUT, /* 8: RAM_ID4 */
PCH_GPIO_INPUT, /* 9: RAM_ID1 */
PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
PCH_GPIO_UNUSED, /* 11: UNUSED */
PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
PCH_GPIO_INPUT, /* 13: RAM_ID0 */
PCH_GPIO_INPUT, /* 14: EC_IN_RW */
PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
PCH_GPIO_UNUSED, /* 16: UNUSED */
PCH_GPIO_UNUSED, /* 17: UNUSED */
PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
PCH_GPIO_UNUSED, /* 19: UNUSED */
PCH_GPIO_UNUSED, /* 20: UNUSED */
PCH_GPIO_UNUSED, /* 21: UNUSED */
PCH_GPIO_UNUSED, /* 22: UNUSED */
PCH_GPIO_UNUSED, /* 23: UNUSED */
PCH_GPIO_UNUSED, /* 24: UNUSED */
PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
PCH_GPIO_UNUSED, /* 26: UNUSED */
PCH_GPIO_UNUSED, /* 27: UNUSED */
PCH_GPIO_UNUSED, /* 28: UNUSED */
PCH_GPIO_UNUSED, /* 29: UNUSED */
PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
PCH_GPIO_UNUSED, /* 37: UNUSED */
PCH_GPIO_UNUSED, /* 38: UNUSED */
PCH_GPIO_UNUSED, /* 39: UNUSED */
PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
PCH_GPIO_UNUSED, /* 41: UNUSED */
PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
PCH_GPIO_UNUSED, /* 43: UNUSED */
PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
PCH_GPIO_INPUT, /* 47: RAM_ID2 */
PCH_GPIO_UNUSED, /* 48: UNUSED */
PCH_GPIO_UNUSED, /* 49: UNUSED */
PCH_GPIO_UNUSED, /* 50: UNUSED */
PCH_GPIO_UNUSED, /* 51: UNUSED */
PCH_GPIO_UNUSED, /* 52: UNUSED */
PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
PCH_GPIO_UNUSED, /* 55: UNUSED */
PCH_GPIO_UNUSED, /* 56: UNUSED */
PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
PCH_GPIO_UNUSED, /* 59: UNUSED */
PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
PCH_GPIO_UNUSED, /* 61: UNUSED */
PCH_GPIO_UNUSED, /* 62: UNUSED */
PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
PCH_GPIO_UNUSED, /* 64: UNUSED */
PCH_GPIO_UNUSED, /* 65: UNUSED */
PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
PCH_GPIO_UNUSED, /* 67: UNUSED */
PCH_GPIO_UNUSED, /* 68: UNUSED */
PCH_GPIO_UNUSED, /* 69: UNUSED */
PCH_GPIO_UNUSED, /* 70: UNUSED */
PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
PCH_GPIO_UNUSED, /* 76: UNUSED */
PCH_GPIO_UNUSED, /* 77: UNUSED */
PCH_GPIO_UNUSED, /* 78: UNUSED */
PCH_GPIO_UNUSED, /* 79: UNUSED */
PCH_GPIO_UNUSED, /* 80: UNUSED */
PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
PCH_GPIO_UNUSED, /* 83: UNUSED */
PCH_GPIO_UNUSED, /* 84: UNUSED */
PCH_GPIO_UNUSED, /* 85: UNUSED */
PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
PCH_GPIO_UNUSED, /* 87: UNUSED */
PCH_GPIO_UNUSED, /* 88: UNUSED */
PCH_GPIO_UNUSED, /* 89: UNUSED */
PCH_GPIO_UNUSED, /* 90: UNUSED */
PCH_GPIO_UNUSED, /* 91: UNUSED */
PCH_GPIO_UNUSED, /* 92: UNUSED */
PCH_GPIO_UNUSED, /* 93: UNUSED */
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};
#endif

112
src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
0x10ec0283, // Subsystem ID
0x0000000e, // Number of jacks (NID entries)
0x0017ff00, // Function Reset
0x0017ff00, // Double Function Reset
0x000F0000, // Pad - get vendor id
0x000F0002, // Pad - get revision id
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
AZALIA_SUBVENDOR(0x0, 0x11790670),
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) DMIC - Internal MIC */
// group 3, cap 0
// no connector, no jack detect
// mic in, digital
// fixed function, internal
AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130),
/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
// group 1, cap 0
// no connector, no jack detect
// speaker out, analog
// fixed function, internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
/* Pin Complex (NID 0x17) MONO Out - Disabled */
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
/* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */
AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
// group2, cap 0
// black, jack detect
// Mic in, 3.5mm Jack
// connector, External left panel
AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
/* Pin Complex (NID 0x1A) LINE1 - Disabled */
AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
/* Pin Complex (NID 0x1B) LINE2 - Disabled */
AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
/* Pin Complex (NID 0x1D) PCBeep */
// eapd low on ex-amp, laptop, custom enable
// mute spkr on hpout
// pcbeep en able, checksum
// no physical, Internal, Location N/A
AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
// group2, cap 1
// black, jack detect
// HPOut, 3.5mm Jack
// connector, left panel
AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
/* Undocumented settings from Realtek (needed for beep_gen) */
/* Widget node 0x20 */
0x02050010,
0x02040c20,
0x0205001b,
0x0204081b,
/* Tuned jack detection */
0x02050043,
0x0204A614,
0x02050047,
0x02049470,
};
const u32 pc_beep_verbs[] = {
0x00170500, /* power up everything (codec, dac, adc, mixers) */
0x01470740, /* enable speaker out */
0x01470c02, /* set speaker EAPD pin */
0x0143b01f, /* unmute speaker */
0x00c37100, /* unmute mixer nid 0xc input 1 */
0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
};
AZALIA_ARRAY_SIZES;

14
src/mainboard/google/auron/onboard.h → src/mainboard/google/auron/variants/lulu/include/variant/onboard.h
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@ -16,22 +16,20 @@
#ifndef ONBOARD_H
#define ONBOARD_H
#define BOARD_LIGHTSENSOR_NAME "lightsensor"
#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */
#define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */
#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44
#define BOARD_TRACKPAD_NAME "trackpad"
#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
#define BOARD_TRACKPAD_I2C_ADDR 0x67
#define BOARD_TRACKPAD_GEN5_I2C_ADDR 0x24
#define BOARD_TRACKPAD_I2C_ADDR 0x2C
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */
#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */
#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */
#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */
#endif

41
src/mainboard/google/auron/variants/lulu/include/variant/spd.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Sage Electronic Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#define SPD_LEN 256
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
/* Lulu board memory configuration GPIOs */
#define SPD_GPIO_BIT0 13
#define SPD_GPIO_BIT1 9
#define SPD_GPIO_BIT2 47
#define SPD_GPIO_BIT3 8
struct pei_data;
void mainboard_fill_spd_data(struct pei_data *pei_data);
#endif

35
src/mainboard/google/auron/variants/lulu/include/variant/thermal.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef THERMAL_H
#define THERMAL_H
/* Control TDP Settings */
#define CTL_TDP_SENSOR_ID 0 /* PECI */
#define CTL_TDP_POWER_LIMIT 12 /* 12W */
#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 104
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 95
/* Tj_max value for calculating PECI CPU temperature */
#define MAX_TEMPERATURE 105
#endif

63
src/mainboard/google/auron/variants/lulu/pei_data.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <string.h>
#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
/* One installed DIMM per channel -- can be changed by SPD init */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* P0: Port B, CN01 (IOBoard) */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0,
USB_PORT_BACK_PANEL);
/* P1: Port A, CN01 */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 2,
USB_PORT_BACK_PANEL);
/* P2: CCD */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
/* P3: BT */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
/* P4: Empty */
pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P5: EMPTY */
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P6: SD Card */
pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_FLEX);
/* P7: EMPTY */
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P0: PORTB*/
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
/* P1: PORTA */
pei_data_usb3_port(pei_data, 1, 1, 2, 0);
/* P2: EMPTY */
pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
/* P3: EMPTY */
pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
}

51
src/mainboard/google/auron/variants/lulu/spd/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
## Copyright (C) 2015 Sage Electronic Engineering
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# { GPIO47, GPIO9, GPIO13, GPIO8}
SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 # 0b0000 2GB
SPD_SOURCES += empty # 0b0001
SPD_SOURCES += empty # 0b0010
SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b0011 2GB
SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 # 0b0100 2GB
SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 # 0b0101 4GB
SPD_SOURCES += empty # 0b0110
SPD_SOURCES += empty # 0b0111
SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 # 0b1000 4GB
SPD_SOURCES += micron_4GiB_dimm_MT41K512M16TNA-125 # 0b1001 8GB
SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA # 0b1010 2GB
SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA # 0b1011 4GB
SPD_SOURCES += hynix_4GiB_dimm_H5TC8G63CMR-PBA # 0b1100 8GB
SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b1101 4GB
SPD_SOURCES += samsung_4GiB_dimm_K4B8G1646Q-MYK0 # 0b1110 8GB
SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
# Include spd rom data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
do printf $$(printf '\%o' 0x$$c); \
done; \
done > $@
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := spd

16
src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex Normal file
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@ -0,0 +1,16 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

32
src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex Normal file
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@ -0,0 +1,32 @@
92 12 0b 03 04 19 02 02
03 52 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 01
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 62 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 ad 01
00 00 00 00 00 00 ff ab
48 4d 54 34 32 35 53 36
41 46 52 36 41 2d 50 42
20 20 4e 30 80 ad 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff

33
src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex Normal file
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@ -0,0 +1,33 @@
# H5TC8G63CMR-PBA
92 13 0b 03 04 19 02 0a
03 52 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 01
00 80 00 00 00 00 00 00
00 88 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 1f 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 ad 01
00 00 00 00 00 00 b2 a3
48 4d 54 38 35 31 53 36
43 4d 52 36 41 2d 50 42
20 20 4e 30 80 ad 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff

32
src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex Normal file
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@ -0,0 +1,32 @@
92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 86
20 08 3c 3c 01 40 83 05
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 01 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 2c 00
00 00 00 00 00 00 19 d2
34 4b 54 46 32 35 36 36
34 48 5a 2d 31 47 36 45
31 20 45 31 80 2c 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff

33
src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex Normal file
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@ -0,0 +1,33 @@
# MT41K512M16TNA-125:E
92 11 0b 03 04 19 02 0A
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 05
00 80 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 2c 00
00 00 00 00 00 00 7f c1
38 4b 54 53 35 31 32 36
34 48 44 5a 2d 31 47 36
45 31 45 31 80 2c 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff

17
src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex Normal file
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@ -0,0 +1,17 @@
# Samsung K4B4G1646E-BYK0
92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F
4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30
20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

17
src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex Normal file
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@ -0,0 +1,17 @@
# Samsung K4B4G1646Q-HYK0
92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9
4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30
20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

17
src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex Normal file
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@ -0,0 +1,17 @@
# Samsung K4B8G1646Q-MYK0
92 12 0B 03 04 19 02 0A 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 80 00 00 00 00 00 00 00 88 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 1F 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00
4D 34 37 31 42 35 31 37 34 51 4D 30 2D 59 4B 30
20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

139
src/mainboard/google/auron/variants/lulu/spd/spd.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Sage Electronic Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbfs.h>
#include <console/console.h>
#include <endian.h>
#include <string.h>
#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron/ec.h>
#include <variant/gpio.h>
#include <variant/spd.h>
static void mainboard_print_spd_info(uint8_t spd[])
{
const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
char spd_name[SPD_PART_LEN+1] = { 0 };
int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
/* Module type */
printk(BIOS_INFO, "SPD: module type is ");
switch (spd[SPD_DRAM_TYPE]) {
case SPD_DRAM_DDR3:
printk(BIOS_INFO, "DDR3\n");
break;
case SPD_DRAM_LPDDR3:
printk(BIOS_INFO, "LPDDR3\n");
break;
default:
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
break;
}
/* Module Part Number */
memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
spd_name[SPD_PART_LEN] = 0;
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
, banks, ranks, rows, cols);
printk(BIOS_INFO, "density %d Mb\n", capmb);
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
devw, busw);
if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
capmb / 8 * busw / devw * ranks);
}
}
/* Copy SPD data for on-board memory */
void mainboard_fill_spd_data(struct pei_data *pei_data)
{
int spd_bits[4] = {
SPD_GPIO_BIT0,
SPD_GPIO_BIT1,
SPD_GPIO_BIT2,
SPD_GPIO_BIT3
};
int spd_gpio[4];
int spd_index;
size_t spd_file_len;
char *spd_file;
spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
spd_gpio[3] = get_gpio(SPD_GPIO_BIT3);
spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) |
(spd_gpio[1] << 1) | spd_gpio[0];
printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
spd_index,
spd_bits[3], spd_gpio[3],
spd_bits[2], spd_gpio[2],
spd_bits[1], spd_gpio[1],
spd_bits[0], spd_gpio[0]);
spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
if (!spd_file)
die("SPD data not found.");
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spd_index = 0;
}
if (spd_file_len < SPD_LEN)
die("Missing SPD data.");
/* CH0 */
memcpy(pei_data->spd_data[0][0],
spd_file + (spd_index * SPD_LEN), SPD_LEN);
/* CH1 not used in 2GB configurations */
if (!((spd_index == 0b0000) || (spd_index == 0b0011) ||
(spd_index == 0b1010))) {
memcpy(pei_data->spd_data[1][0],
spd_file + (spd_index * SPD_LEN), SPD_LEN);
}
/* Make sure a valid SPD was found */
if (pei_data->spd_data[0][0][0] == 0)
die("Invalid SPD data.");
mainboard_print_spd_info(pei_data->spd_data[0][0]);
}

48
src/mainboard/google/auron/variants/lulu/variant.c Normal file
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@ -0,0 +1,48 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <smbios.h>
#include <soc/romstage.h>
#include <variant/onboard.h>
#include <mainboard/google/auron/variant.h>
int variant_smbios_data(device_t dev, int *handle,
unsigned long *current)
{
int len = 0;
len += smbios_write_type41(
current, handle,
BOARD_TRACKPAD_NAME, /* name */
BOARD_TRACKPAD_IRQ, /* instance */
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
len += smbios_write_type41(
current, handle,
BOARD_TOUCHSCREEN_NAME, /* name */
BOARD_TOUCHSCREEN_IRQ, /* instance */
BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
return len;
}
void variant_romstage_entry(struct romstage_params *rp)
{
/* N/A for boards other than SAMUS */
}

14
src/mainboard/google/samus/Makefile.inc → src/mainboard/google/auron/variants/samus/Makefile.inc
View File

@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
@ -13,17 +11,5 @@
## GNU General Public License for more details.
##
subdirs-y += spd
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += chromeos.c
ramstage-y += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += pei_data.c
ramstage-y += pei_data.c
romstage-y += board_version.c
ramstage-y += board_version.c

22
src/mainboard/google/samus/board_version.c → src/mainboard/google/auron/variants/samus/board_version.c
View File

@ -14,20 +14,20 @@
*/
#include <ec/google/chromeec/ec.h>
#include "board_version.h"
#include <variant/board_version.h>
const char *samus_board_version(void)
{
switch (google_chromeec_get_board_version()) {
case SAMUS_EC_BOARD_VERSION_EVT1:
return "EVT1";
case SAMUS_EC_BOARD_VERSION_EVT2:
return "EVT2";
case SAMUS_EC_BOARD_VERSION_EVT3:
return "EVT3";
case SAMUS_EC_BOARD_VERSION_EVT4:
return "EVT4";
default:
return "Unknown";
case SAMUS_EC_BOARD_VERSION_EVT1:
return "EVT1";
case SAMUS_EC_BOARD_VERSION_EVT2:
return "EVT2";
case SAMUS_EC_BOARD_VERSION_EVT3:
return "EVT3";
case SAMUS_EC_BOARD_VERSION_EVT4:
return "EVT4";
default:
return "Unknown";
}
}

0
src/mainboard/google/samus/devicetree.cb → src/mainboard/google/auron/variants/samus/devicetree.cb
View File

168
src/mainboard/google/samus/acpi/mainboard.asl → src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl
View File

@ -15,92 +15,8 @@
#undef ENABLE_TOUCH_WAKE
Scope (\_SB)
{
Device (LID0)
{
Name (_HID, EisaId("PNP0C0D"))
Method (_LID, 0)
{
Return (\_SB.PCI0.LPCB.EC0.LIDS)
}
// EC wake is GPIO27 which is a special DeepSX wake pin
Name (_PRW, Package(){ 0x70, 5 }) // GP27_EN
}
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
}
/*
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
/*
* WLAN connected to Root Port 3, becomes Root Port 1 after coalesce
*/
Scope (\_SB.PCI0.RP01)
{
Device (WLAN)
{
Name (_ADR, 0x00000000)
/* GPIO10 is PCH_WLAN_WAKE_L */
Name (GPIO, 10)
Name (_PRW, Package() { GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
}
}
}
}
Scope (\_SB.PCI0.I2C0)
{
Device (ATPB)
{
Name (_HID, "ATML0000")
Name (_DDN, "Atmel Touchpad Bootloader")
Name (_UID, 1)
Name (_S0W, 4)
Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x26, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
// GPIO13 is PIRQL
Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 }
})
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
}
Device (ATPA)
{
Name (_HID, "ATML0000")
@ -108,29 +24,29 @@ Scope (\_SB.PCI0.I2C0)
Name (_UID, 2)
Name (_S0W, 4)
Name (ISTP, 1) /* Touchpad */
Name (GPIO, 9) /* TRACKPAD_INT_L (WAKE) */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x4a, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
// GPIO13 is PIRQL
Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 }
Interrupt (ResourceConsumer, Level, ActiveLow) { 27 }
})
Name (_PRW, Package() { GPIO, 3 })
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
@ -153,7 +69,6 @@ Scope (\_SB.PCI0.I2C0)
Name (_HID, "RT5677CE")
Name (_DDN, "RT5667 Codec")
Name (_UID, 1)
Name (WAKE, 45) /* DSP_INT (use as codec wake) */
Name (MB1, 1) /* MICBIAS1 = 2.970V */
Name (DACR, 1) /* Use codec internal 1.8V as DACREF source */
@ -194,11 +109,11 @@ Scope (\_SB.PCI0.I2C0)
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x2c, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
BOARD_CODEC_I2C_ADDR, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
/* GPIO46 is PIRQO (use HOTWORD_DET as codec IRQ) */
@ -235,13 +150,14 @@ Scope (\_SB.PCI0.I2C0)
"\\_SB.PCI0.I2C0.CODC") { 1 }
})
Name (_PRW, Package() { WAKE, 3 })
Name (_PRW, Package() { BOARD_CODEC_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_CODEC_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (^WAKE)
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
@ -258,38 +174,6 @@ Scope (\_SB.PCI0.I2C0)
Scope (\_SB.PCI0.I2C1)
{
Device (ATSB)
{
Name (_HID, "ATML0001")
Name (_DDN, "Atmel Touchscreen Bootloader")
Name (_UID, 4)
Name (_S0W, 4)
Name (ISTP, 0) /* TouchScreen */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x27, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C1", // ResourceSource
)
// GPIO14 is PIRQM
Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 }
})
Method (_STA)
{
If (LEqual (\S2EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
}
Device (ATSA)
{
Name (_HID, "ATML0001")
@ -297,30 +181,30 @@ Scope (\_SB.PCI0.I2C1)
Name (_UID, 5)
Name (_S0W, 4)
Name (ISTP, 0) /* TouchScreen */
Name (GPIO, 14) /* TOUCH_INT_L */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x4b, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C1", // ResourceSource
BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C1", // ResourceSource
)
// GPIO14 is PIRQM
Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 }
Interrupt (ResourceConsumer, Level, ActiveLow) { 28 }
})
#ifdef ENABLE_TOUCH_WAKE
Name (_PRW, Package() { GPIO, 3 })
Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_CODEC_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
#endif

0
src/mainboard/google/samus/board_version.h → src/mainboard/google/auron/variants/samus/include/variant/board_version.h
View File

5
src/mainboard/google/samus/gpio.h → src/mainboard/google/auron/variants/samus/include/variant/gpio.h
View File

@ -18,11 +18,6 @@
#include <soc/gpio.h>
#define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23
#define SAMUS_GPIO_SSD_RESET_L 47
#define SAMUS_GPIO_WLAN_DISABLE_L 42
#define SAMUS_GPIO_LTE_DISABLE_L 59
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */

0
src/mainboard/google/samus/hda_verb.c → src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h
View File

32
src/mainboard/google/auron/variants/samus/include/variant/onboard.h Normal file
View File

@ -0,0 +1,32 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef ONBOARD_H
#define ONBOARD_H
#define BOARD_TRACKPAD_I2C_ADDR 0x4a
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4b
#define BOARD_CODEC_I2C_ADDR 0x2c
#define BOARD_TRACKPAD_WAKE_GPIO 9 /* GPIO9 */
#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
#define BOARD_TOUCHSCREEN_WAKE_GPIO 14 /* GPIO14 */
#define BOARD_PP3300_AUTOBAHN_GPIO 23 /* GPIO23 */
#define BOARD_WLAN_DISABLE_GPIO 42 /* GPIO42 */
#define BOARD_CODEC_WAKE_GPIO 45 /* GPIO45 */
#define BOARD_SSD_RESET_GPIO 47 /* GPIO47 */
#define BOARD_LTE_DISABLE_GPIO 59 /* GPIO59 */
#endif

6
src/mainboard/google/samus/spd/spd.h → src/mainboard/google/auron/variants/samus/include/variant/spd.h
View File

@ -19,14 +19,14 @@
#define SPD_LEN 256
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
#define SPD_PART_LEN 18
/* Samus board memory configuration GPIOs */
#define SPD_GPIO_BIT0 69

7
src/mainboard/google/samus/thermal.h → src/mainboard/google/auron/variants/samus/include/variant/thermal.h
View File

@ -16,7 +16,12 @@
#ifndef THERMAL_H
#define THERMAL_H
#define TEMPERATURE_SENSOR_ID 0 /* PECI */
/* Control TDP Settings */
#define CTL_TDP_SENSOR_ID 0 /* PECI */
#define CTL_TDP_POWER_LIMIT 12 /* 12W */
#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 104

0
src/mainboard/google/samus/pei_data.c → src/mainboard/google/auron/variants/samus/pei_data.c
View File

34
src/mainboard/google/samus/spd/Makefile.inc → src/mainboard/google/auron/variants/samus/spd/Makefile.inc
View File

@ -18,24 +18,24 @@ romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# { GPIO65, GPIO67, GPIO68, GPIO69 }
SPD_SOURCES = empty # 0b0000
SPD_SOURCES += empty # 0b0001
SPD_SOURCES += empty # 0b0010
SPD_SOURCES += empty # 0b0011
SPD_SOURCES += empty # 0b0100
SPD_SOURCES += empty # 0b0101
SPD_SOURCES += samsung_4 # 0b0110
SPD_SOURCES += empty # 0b0111
SPD_SOURCES += hynix_4 # 0b1000
SPD_SOURCES += empty # 0b1001
SPD_SOURCES += samsung_8 # 0b1010
SPD_SOURCES += empty # 0b1011
SPD_SOURCES += hynix_8 # 0b1100
SPD_SOURCES += hynix_16 # 0b1101
SPD_SOURCES += empty # 0b1110
SPD_SOURCES += elpida_16 # 0b1111
SPD_SOURCES = empty # 0b0000
SPD_SOURCES += empty # 0b0001
SPD_SOURCES += empty # 0b0010
SPD_SOURCES += empty # 0b0011
SPD_SOURCES += empty # 0b0100
SPD_SOURCES += empty # 0b0101
SPD_SOURCES += samsung_4 # 0b0110
SPD_SOURCES += empty # 0b0111
SPD_SOURCES += hynix_4 # 0b1000
SPD_SOURCES += empty # 0b1001
SPD_SOURCES += samsung_8 # 0b1010
SPD_SOURCES += empty # 0b1011
SPD_SOURCES += hynix_8 # 0b1100
SPD_SOURCES += hynix_16 # 0b1101
SPD_SOURCES += empty # 0b1110
SPD_SOURCES += elpida_16 # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)

0
src/mainboard/google/samus/spd/elpida_16.spd.hex → src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex
View File

0
src/mainboard/google/samus/spd/elpida_4.spd.hex → src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex
View File

0
src/mainboard/google/samus/spd/elpida_8.spd.hex → src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex
View File

16
src/mainboard/google/auron/variants/samus/spd/empty.spd.hex Normal file
View File

@ -0,0 +1,16 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0
src/mainboard/google/samus/spd/hynix_16.spd.hex → src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex
View File

0
src/mainboard/google/samus/spd/hynix_4.spd.hex → src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex
View File

0
src/mainboard/google/samus/spd/hynix_8.spd.hex → src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex
View File

0
src/mainboard/google/samus/spd/samsung_4.spd.hex → src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex
View File

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