mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency

All the boards in the patch have a constraint for the I2C bus to operate
on 100 kHz. Provide dedicated values for rise time, fall time and data
hold time on mainboard level to get a proper timing which takes the bus
load into account. Giving these values the driver computes the needed
timings correctly.

TEST=Measure I2C frequency on all boards while coreboot accesses
external RTC and make sure it is 100 kHz.

Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52721
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb

@@ -46,7 +46,10 @@ chip soc/intel/apollolake
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
 		.i2c[0] = {
-			.speed = I2C_SPEED_STANDARD
+			.speed = I2C_SPEED_STANDARD,
+			.rise_time_ns = 160,
+			.fall_time_ns = 110,
+			.data_hold_time_ns = 300
 		},
 	}"
 

src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb

@@ -41,6 +41,16 @@ chip soc/intel/apollolake
 	# Enable Vtd feature
 	register "enable_vtd" = "1"
 
+	# I2C3 controller used for RTC
+	register "common_soc_config" = "{
+		.i2c[3] = {
+			.speed = I2C_SPEED_STANDARD,
+			.rise_time_ns = 60,
+			.fall_time_ns = 20,
+			.data_hold_time_ns = 300
+		},
+	}"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 off end	# - DPTF

src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb

@@ -38,6 +38,16 @@ chip soc/intel/apollolake
 	# 0:HS400(Default), 1:HS200, 2:DDR50
 	register "emmc_host_max_speed" = "1"
 
+	# I2C0 controller used for RTC
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_STANDARD,
+			.rise_time_ns = 40,
+			.fall_time_ns = 10,
+			.data_hold_time_ns = 300
+		},
+	}"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 off end	# - DPTF

src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb

@@ -41,6 +41,16 @@ chip soc/intel/apollolake
 	# Enable Vtd feature
 	register "enable_vtd" = "1"
 
+	# I2C0 controller used for RTC
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_STANDARD,
+			.rise_time_ns = 160,
+			.fall_time_ns = 110,
+			.data_hold_time_ns = 300
+		},
+	}"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 off end	# - DPTF

src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb

@@ -12,6 +12,16 @@ chip soc/intel/apollolake
 	# Enable Vtd feature
 	register "enable_vtd" = "1"
 
+	# I2C0 controller used for RTC
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_STANDARD,
+			.rise_time_ns = 40,
+			.fall_time_ns = 10,
+			.data_hold_time_ns = 300
+		}
+	}"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 off end	# - DPTF