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add cpureginit to romcc code. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-04-10 16:40:19 +00:00
parent 526b2c429e
commit 45f6c5e3d4
5 changed files with 16 additions and 32 deletions
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26
src/cpu/amd/model_gx2/cpureginit.c
View File

@ -1,15 +1,4 @@
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
#include <cpu/amd/gx2def.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
/* ***************************************************************************/
/* **/
@ -79,14 +68,14 @@ BIST(void){
return;
BISTFail:
printk_err("BIST failed!\n");
print_err("BIST failed!\n");
while(1);
}
/* ***************************************************************************/
/* * cpuRegInit*/
/* ***************************************************************************/
void
cpuRegInit (int diagmode){
cpuRegInit (void){
int msrnum;
msr_t msr;
/* Turn on BTM for early debug based on setup. */
@ -196,11 +185,6 @@ cpuRegInit (int diagmode){
msr.lo |= DOTPPL_LOWER_PD_SET;
wrmsr(msrnum, msr);
/* */
/* Set the Delay Control in GLCP*/
/* */
/* SetDelayControl();*/
/* */
/* Enable RSDC*/
/* */
@ -215,7 +199,7 @@ cpuRegInit (int diagmode){
/* */
/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
{
BIST();
// BIST();
}
@ -303,6 +287,6 @@ MTestPinCheckBX (void){
}
/* Lock the cache down here.*/
wbinvd();
__asm__("wbinvd\n");
}

2
src/cpu/amd/model_gx2/model_gx2_init.c
View File

@ -73,8 +73,6 @@ unsigned long addr;
}
#endif
#include "cpureginit.c"
static void model_gx2_init(device_t dev)
{
void do_vsmbios(void);

6
src/include/cpu/amd/gx2def.h
View File

@ -69,11 +69,11 @@
#define GL0_DF 6
#define GL1_GLIU0 1
#define GL1_GLCP 3
#define GL1_GLCP 3
#define GL1_PCI 4
#define GL1_FG 5
#define GL1_VIP 5
#define GL1_AES 6
#define GL1_VIP 5
#define GL1_AES 6
#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29)

5
src/mainboard/amd/rumba/auto.c
View File

@ -100,6 +100,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
static void msr_init(void)
{
@ -153,8 +154,8 @@ static void main(unsigned long bist)
pll_reset();
/* Halt if there was a built in self test failure */
//report_bist_failure(bist);
cpuRegInit();
print_err("done cpuRegInit\n");
sdram_initialize(1, memctrl);

7
src/mainboard/lippert/frontrunner/auto.c
View File

@ -47,7 +47,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
static void msr_init(void)
{
@ -92,8 +92,9 @@ static void main(unsigned long bist)
print_err("done cs5535 early\n");
pll_reset();
print_err("done pll_reset\n");
/* Halt if there was a built in self test failure */
//report_bist_failure(bist);
cpuRegInit();
print_err("done cpuRegInit\n");
sdram_initialize(1, memctrl);