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mb/google/brya/var/agah: Modify GPP_A8 programming 

The EEs noticed this pin was misbehaving; it was accidentally set to a
low output, but should be open-drain (NC). This patch fixes that.

BUG=b:237837108
TEST=verified by EEs

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tim Wawrzynczak 2022-07-27 12:17:51 -06:00 committed by Paul Fagerburg
parent 86b517f88e
commit 460fea6523
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/brya/variants/agah/gpio.c
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@ -10,7 +10,7 @@ static const struct pad_config override_gpio_table[] = {
/* A7 : SRCCLK_OE7# ==> LAN_WAKE_ODL */ /* A7 : SRCCLK_OE7# ==> LAN_WAKE_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE), PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE),
/* A8 : SRCCLKREQ7# ==> USB2_A2_RT_RST_ODL */ /* A8 : SRCCLKREQ7# ==> USB2_A2_RT_RST_ODL */
PAD_CFG_GPO(GPP_A8, 1, DEEP), PAD_NC(GPP_A8, NONE),
/* A12 : SATAXPCIE1 ==> EN_PP3300_LAN_X */ /* A12 : SATAXPCIE1 ==> EN_PP3300_LAN_X */
PAD_CFG_GPO(GPP_A12, 1, DEEP), PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A14 : USB_OC1# ==> USB_C0_OC_ODL */ /* A14 : USB_OC1# ==> USB_C0_OC_ODL */