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soc/intel/common: Set controller state to active in uart init 

Set the controller state to D0 during the uart init sequence, this
ensures the controller is up and active.

One more argument struct device *dev has been added
to uart_lpss_init function for the same.

BUG=b:135941367
TEST=Verify no timeouts seen during UART controller enumeration
     sequence in CML and ICL platforms.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0187267670e1dea3e1d5e83d0b29967724d6063e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34447
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Usha P 2019-07-19 14:29:29 +05:30 committed by Subrata Banik
parent 47a7b37cbf
commit 46445155ea
1 changed files with 6 additions and 3 deletions
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9
src/soc/intel/common/block/uart/uart.c
View File

@ -33,8 +33,11 @@
extern const struct uart_gpio_pad_config uart_gpio_pads[]; extern const struct uart_gpio_pad_config uart_gpio_pads[];
extern const int uart_max_index; extern const int uart_max_index;
static void uart_lpss_init(uintptr_t baseaddr) static void uart_lpss_init(struct device *dev, uintptr_t baseaddr)
{ {
/* Ensure controller is in D0 state */
lpss_set_power_state(dev, STATE_D0);
/* Take UART out of reset */ /* Take UART out of reset */
lpss_reset_release(baseaddr); lpss_reset_release(baseaddr);
@ -81,7 +84,7 @@ void uart_common_init(struct device *device, uintptr_t baseaddr)
/* Enable memory access and bus master */ /* Enable memory access and bus master */
pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE); pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE);
uart_lpss_init(baseaddr); uart_lpss_init(device, baseaddr);
} }
struct device *uart_get_device(void) struct device *uart_get_device(void)
@ -224,7 +227,7 @@ static void uart_common_enable_resources(struct device *dev)
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF;
if (base) if (base)
uart_lpss_init(base); uart_lpss_init(dev, base);
} }
} }