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device/pci_ops: Have only default PCI bus ops available 

In the current state of the tree we do not utilise the
mechanism of having per-device overrides for PCI bus
ops.

This change effectively inlines all PCI config accessors
for ramstage as well.

Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-03-07 14:18:28 +02:00
parent 34cf5619f9
commit 4663f45caa
9 changed files with 7 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/x86/Makefile.inc
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@ -327,8 +327,6 @@ ramstage-y += memmove.c
ramstage-y += memset.c ramstage-y += memset.c
ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
ramstage-y += pci_ops_conf1.c
ramstage-$(CONFIG_NO_MMCONF_SUPPORT) += pci_ops.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
ramstage-y += rdrand.c ramstage-y += rdrand.c
ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c

6
src/arch/x86/include/arch/pci_ops.h
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@ -17,10 +17,4 @@
#include <arch/pci_io_cfg.h> #include <arch/pci_io_cfg.h>
#include <device/pci_mmio_cfg.h> #include <device/pci_mmio_cfg.h>
#ifndef __SIMPLE_DEVICE__
extern const struct pci_bus_operations pci_cf8_conf1;
#endif
#endif /* ARCH_I386_PCI_OPS_H */ #endif /* ARCH_I386_PCI_OPS_H */

22
src/arch/x86/pci_ops.c
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@ -1,22 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci_ops.h>
const struct pci_bus_operations *pci_bus_default_ops(void)
{
return &pci_cf8_conf1;
}

30
src/arch/x86/pci_ops_conf1.c
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@ -1,30 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <arch/pci_io_cfg.h>
/*
* Functions for accessing PCI configuration space with type 1 accesses
*/
const struct pci_bus_operations pci_cf8_conf1 = {
.read8 = pci_io_read_config8,
.read16 = pci_io_read_config16,
.read32 = pci_io_read_config32,
.write8 = pci_io_write_config8,
.write16 = pci_io_write_config16,
.write32 = pci_io_write_config32,
};

1
src/device/Makefile.inc
View File

@ -33,7 +33,6 @@ ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
endif endif
subdirs-y += oprom dram subdirs-y += oprom dram

39
src/device/pci_ops_mmconf.c
View File

@ -1,39 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_mmio_cfg.h>
#if (CONFIG_MMCONF_BASE_ADDRESS == 0)
#error "CONFIG_MMCONF_BASE_ADDRESS needs to be non-zero!"
#endif
/*
* Functions for accessing PCI configuration space with mmconf accesses
*/
static const struct pci_bus_operations pci_ops_mmconf = {
.read8 = pci_mmio_read_config8,
.read16 = pci_mmio_read_config16,
.read32 = pci_mmio_read_config32,
.write8 = pci_mmio_write_config8,
.write16 = pci_mmio_write_config16,
.write32 = pci_mmio_write_config32,
};
const struct pci_bus_operations *pci_bus_default_ops(void)
{
return &pci_ops_mmconf;
}

1
src/include/device/device.h
View File

@ -17,7 +17,6 @@
struct device; struct device;
struct pci_operations; struct pci_operations;
struct pci_bus_operations;
struct i2c_bus_operations; struct i2c_bus_operations;
struct smbus_bus_operations; struct smbus_bus_operations;
struct pnp_mode_ops; struct pnp_mode_ops;

14
src/include/device/pci.h
View File

@ -22,6 +22,7 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/resource.h> #include <device/resource.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci_ops.h>
#include <device/pci_rom.h> #include <device/pci_rom.h>
#include <device/pci_type.h> #include <device/pci_type.h>
@ -33,19 +34,6 @@ struct pci_operations {
void (*set_L1_ss_latency)(struct device *dev, unsigned int off); void (*set_L1_ss_latency)(struct device *dev, unsigned int off);
}; };
/* Common pci bus operations */
struct pci_bus_operations {
uint8_t (*read8)(pci_devfn_t dev, uint16_t reg);
uint16_t (*read16)(pci_devfn_t dev, uint16_t reg);
uint32_t (*read32)(pci_devfn_t dev, uint16_t reg);
void (*write8)(pci_devfn_t dev, uint16_t reg, uint8_t val);
void (*write16)(pci_devfn_t dev, uint16_t reg, uint16_t val);
void (*write32)(pci_devfn_t dev, uint16_t reg, uint32_t val);
};
// FIXME: Needs complete pci_bus_operations
#include <device/pci_ops.h>
struct pci_driver { struct pci_driver {
const struct device_operations *ops; const struct device_operations *ops;
unsigned short vendor; unsigned short vendor;

25
src/include/device/pci_ops.h
View File

@ -39,13 +39,6 @@
#include <device/pci.h> #include <device/pci.h>
const struct pci_bus_operations *pci_bus_default_ops(void);
static __always_inline const struct pci_bus_operations *pci_bus_ops(void)
{
return pci_bus_default_ops();
}
void __noreturn pcidev_die(void); void __noreturn pcidev_die(void);
static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev)
@ -63,43 +56,37 @@ static __always_inline pci_devfn_t pcidev_assert(const struct device *dev)
static __always_inline static __always_inline
u8 pci_read_config8(const struct device *dev, u16 reg) u8 pci_read_config8(const struct device *dev, u16 reg)
{ {
pci_devfn_t bdf = PCI_BDF(dev); return pci_s_read_config8(PCI_BDF(dev), reg);
return pci_bus_ops()->read8(bdf, reg);
} }
static __always_inline static __always_inline
u16 pci_read_config16(const struct device *dev, u16 reg) u16 pci_read_config16(const struct device *dev, u16 reg)
{ {
pci_devfn_t bdf = PCI_BDF(dev); return pci_s_read_config16(PCI_BDF(dev), reg);
return pci_bus_ops()->read16(bdf, reg);
} }
static __always_inline static __always_inline
u32 pci_read_config32(const struct device *dev, u16 reg) u32 pci_read_config32(const struct device *dev, u16 reg)
{ {
pci_devfn_t bdf = PCI_BDF(dev); return pci_s_read_config32(PCI_BDF(dev), reg);
return pci_bus_ops()->read32(bdf, reg);
} }
static __always_inline static __always_inline
void pci_write_config8(const struct device *dev, u16 reg, u8 val) void pci_write_config8(const struct device *dev, u16 reg, u8 val)
{ {
pci_devfn_t bdf = PCI_BDF(dev); pci_s_write_config8(PCI_BDF(dev), reg, val);
pci_bus_ops()->write8(bdf, reg, val);
} }
static __always_inline static __always_inline
void pci_write_config16(const struct device *dev, u16 reg, u16 val) void pci_write_config16(const struct device *dev, u16 reg, u16 val)
{ {
pci_devfn_t bdf = PCI_BDF(dev); pci_s_write_config16(PCI_BDF(dev), reg, val);
pci_bus_ops()->write16(bdf, reg, val);
} }
static __always_inline static __always_inline
void pci_write_config32(const struct device *dev, u16 reg, u32 val) void pci_write_config32(const struct device *dev, u16 reg, u32 val)
{ {
pci_devfn_t bdf = PCI_BDF(dev); pci_s_write_config32(PCI_BDF(dev), reg, val);
pci_bus_ops()->write32(bdf, reg, val);
} }
#endif #endif