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pcengines/apu1: Add CMOS/NVRAM support 

Inspired by the Sage source code (itself from coreboot).

Change-Id: I4864923166efb200882d895c572d1ee060c71951
Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com>
Reviewed-on: http://review.coreboot.org/11730
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Maxime de Roucy 2015-09-27 15:45:35 +02:00 committed by Alexandru Gagniuc
parent 9595ed4731
commit 46731237ce
3 changed files with 53 additions and 0 deletions
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2
src/mainboard/pcengines/apu1/Kconfig
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@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select BOARD_ROMSIZE_KB_2048
select SPD_CACHE

5
src/mainboard/pcengines/apu1/cmos.default Normal file
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@ -0,0 +1,5 @@
last_boot=Fallback
boot_option=Fallback
multi_core=Enable
debug_level=Spew
baud_rate=115200

46
src/mainboard/pcengines/apu1/cmos.layout Normal file
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@ -0,0 +1,46 @@
entries
# <start-bit> <bit-length> <config> <config-id> <parameter-name>
0 384 r 0 reserved_memory
384 4 r 0 reboot_bits
388 1 e 2 last_boot
# leave 3 bits to make checksummed area start byte-aligned
392 1 e 2 boot_option
393 1 e 1 multi_core
394 3 e 3 baud_rate
397 4 e 4 debug_level
# leave 7 bits to make checksummed area end byte-aligned
408 16 h 0 check_sum
enumerations
#<config-id> <value> <label>
## for multi_core
1 0 Enable
1 1 Disable
## for last_boot, boot_option
2 0 Fallback
2 1 Normal
## for baud_rate
3 0 115200
3 1 57600
3 2 38400
3 3 19200
3 4 9600
3 5 4800
3 6 2400
3 7 1200
## for debug_level
4 0 Emerg
4 1 Alert
4 2 Crit
4 3 Err
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
checksums
checksum 392 407 408