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no warnings days. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-25 14:37:18 +00:00 committed by Stefan Reinauer
parent d55e26f1b1
commit 467a065384
14 changed files with 59 additions and 109 deletions
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33
src/drivers/ati/ragexl/atyfb.h
View File

@ -1,24 +1,11 @@
/*
* ATI Frame Buffer Device Driver Core Definitions
*/
#define u32 uint32_t
#define u16 uint16_t
#define u8 uint8_t
#define u_int uint32_t
#define PLL_CRTC_DECODE 0
#define EINVAL -1
#define readb(addr) (*(volatile unsigned char *) (addr))
#define readw(addr) (*(volatile unsigned short *) (addr))
#define readl(addr) (*(volatile unsigned int *) (addr))
#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b))
#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b))
#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b))
#define max(x,y) (x>=y)?x:y
#if CONFIG_CONSOLE_BTEXT==1
@ -226,7 +213,7 @@ static inline u32 aty_ld_le32(int regindex,
#ifdef ATARI
return in_le32((volatile u32 *)(info->ati_regbase+regindex));
#else
return readl (info->ati_regbase + regindex);
return read32 (info->ati_regbase + regindex);
#endif
}
@ -240,7 +227,7 @@ static inline void aty_st_le32(int regindex, u32 val,
#ifdef ATARI
out_le32 (info->ati_regbase+regindex, val);
#else
writel (val, info->ati_regbase + regindex);
write32 (info->ati_regbase + regindex, val);
#endif
}
@ -254,7 +241,7 @@ static inline u16 aty_ld_le16(int regindex,
#if defined(__mc68000__)
return le16_to_cpu(*((volatile u16 *)(info->ati_regbase+regindex)));
#else
return readw (info->ati_regbase + regindex);
return read16 (info->ati_regbase + regindex);
#endif
}
@ -268,7 +255,7 @@ static inline void aty_st_le16(int regindex, u16 val,
#if defined(__mc68000__)
*((volatile u16 *)(info->ati_regbase+regindex)) = cpu_to_le16(val);
#else
writew (val, info->ati_regbase + regindex);
write16 (info->ati_regbase + regindex, val);
#endif
}
@ -282,7 +269,7 @@ static inline u8 aty_ld_8(int regindex,
#ifdef ATARI
return in_8 (info->ati_regbase + regindex);
#else
return readb (info->ati_regbase + regindex);
return read8 (info->ati_regbase + regindex);
#endif
}
@ -296,7 +283,7 @@ static inline void aty_st_8(int regindex, u8 val,
#ifdef ATARI
out_8 (info->ati_regbase + regindex, val);
#else
writeb (val, info->ati_regbase + regindex);
write8 (info->ati_regbase + regindex, val);
#endif
}
@ -407,8 +394,8 @@ static inline void wait_for_idle(struct fb_info_aty *info)
extern void aty_reset_engine(const struct fb_info_aty *info);
extern void aty_init_engine(const struct atyfb_par *par,
struct fb_info_aty *info);
extern void aty_rectfill(int dstx, int dsty, u_int width, u_int height,
u_int color, struct fb_info_aty *info);
extern void aty_rectfill(int dstx, int dsty, u32 width, u32 height,
u32 color, struct fb_info_aty *info);
/*

37
src/drivers/ati/ragexl/fbcon.h
View File

@ -11,11 +11,8 @@
#ifndef _VIDEO_FBCON_H
#define _VIDEO_FBCON_H
struct display {
/* Filled in by the frame buffer device */
struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */
/* are updated by fbcon.c */
struct fb_cmap cmap; /* colormap */
@ -29,19 +26,10 @@ struct display {
u32 line_length; /* length of a line in bytes */
u16 can_soft_blank; /* zero if no hardware blanking */
u16 inverse; /* != 0 text black on white as default */
// struct display_switch *dispsw; /* low level operations */
// void *dispsw_data; /* optional dispsw helper data */
#if 0
struct fb_fix_cursorinfo fcrsr;
struct fb_var_cursorinfo *vcrsr;
struct fb_cursorstate crsrstate;
#endif
/* Filled in by the low-level console driver */
struct vc_data *conp; /* pointer to console data */
// struct fb_info *fb_info; /* frame buffer for this console */
int vrows; /* number of virtual rows */
unsigned short cursor_x; /* current cursor position */
unsigned short cursor_y;
@ -148,29 +136,4 @@ struct display {
/* Namespace consistency */
#define SCROLL_YNOPARTIAL __SCROLL_YNOPARTIAL
#if defined(__i386__) || defined(__alpha__) || \
defined(__x86_64__) || defined(__hppa__) || \
defined(__powerpc64__)
#define fb_readb __raw_readb
#define fb_readw __raw_readw
#define fb_readl __raw_readl
#define fb_writeb __raw_writeb
#define fb_writew __raw_writew
#define fb_writel __raw_writel
#define fb_memset memset_io
#else
#define fb_readb(addr) (*(volatile u8 *) (addr))
#define fb_readw(addr) (*(volatile u16 *) (addr))
#define fb_readl(addr) (*(volatile u32 *) (addr))
#define fb_writeb(b,addr) (*(volatile u8 *) (addr) = (b))
#define fb_writew(b,addr) (*(volatile u16 *) (addr) = (b))
#define fb_writel(b,addr) (*(volatile u32 *) (addr) = (b))
#define fb_memset memset
#endif
#endif /* _VIDEO_FBCON_H */

8
src/drivers/ati/ragexl/xlinit.c
View File

@ -1429,10 +1429,10 @@ static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
#else
scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
#endif
writeb(regno << scale, &info->aty_cmap_regs->windex);
writeb(red, &info->aty_cmap_regs->lut);
writeb(green, &info->aty_cmap_regs->lut);
writeb(blue, &info->aty_cmap_regs->lut);
write8(&info->aty_cmap_regs->windex, regno << scale)
write8(&info->aty_cmap_regs->lut, red);
write8(&info->aty_cmap_regs->lut, green);
write8(&info->aty_cmap_regs->lut, blue);
return 0;
}

12
src/mainboard/intel/jarrell/jarrell_fixups.c
View File

@ -4,7 +4,7 @@ static void mch_reset(void)
{
device_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0);
if (dev != PCI_DEV_INVALID) {
/* I/O space is always enables */
@ -30,8 +30,6 @@ static void mch_reset(void)
return;
}
static void mainboard_set_e7520_pll(unsigned bits)
{
uint16_t gpio_index;
@ -64,14 +62,13 @@ static void mainboard_set_e7520_pll(unsigned bits)
outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
/* reset */
print_debug("set_pllsel: settings adjusted, now resetting...\n");
// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
// mch_reset();
// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
// mch_reset();
full_reset();
}
return;
}
static void mainboard_set_e7520_leds(void)
{
uint8_t cnt;
@ -118,6 +115,3 @@ static void mainboard_set_e7520_leds(void)
return;
}

9
src/mainboard/intel/jarrell/reset.c
View File

@ -1,6 +1,6 @@
#include <arch/io.h>
#include <reset.h>
#include <arch/romcc_io.h>
#include <reset.h>
void soft_reset(void)
{
@ -13,6 +13,11 @@ void hard_reset(void)
outb(0x06, 0xcf9);
}
#ifndef __ROMCC__
/* Used only board-internally by power_reset_check.c and jarell_fixups.c */
void full_reset(void);
#endif
void full_reset(void)
{
/* Enable power on after power fail... */
@ -20,7 +25,7 @@ void full_reset(void)
byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
byte &= 0xfe;
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte);
outb(0x0e, 0xcf9);
}

2
src/mainboard/intel/xe7501devkit/reset.c
View File

@ -1,6 +1,6 @@
#include <reset.h>
void i82801cx_hard_reset(void);
#include "southbridge/intel/i82801cx/i82801cx.h"
void hard_reset(void)
{

9
src/southbridge/amd/amd8111/amd8111_early_smbus.c
View File

@ -26,22 +26,23 @@ static void enable_smbus(void)
print_spew("SMBus controller enabled\n");
}
static int smbus_recv_byte(unsigned device)
static inline int smbus_recv_byte(unsigned device)
{
return do_smbus_recv_byte(SMBUS_IO_BASE, device);
}
static int smbus_send_byte(unsigned device, unsigned char val)
static inline int smbus_send_byte(unsigned device, unsigned char val)
{
return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
static int smbus_read_byte(unsigned device, unsigned address)
static inline int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}

18
src/southbridge/amd/cs5536/cs5536_smbus2.h
View File

@ -253,18 +253,16 @@ static void _doread(unsigned smbus_io_base, unsigned char device,
printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret);
}
static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
unsigned char device,
unsigned char address)
static inline unsigned char do_smbus_read_byte(unsigned smbus_io_base,
unsigned char device, unsigned char address)
{
unsigned char val = 0;
_doread(smbus_io_base, device, address, &val, sizeof(val));
return val;
}
static unsigned short do_smbus_read_word(unsigned smbus_io_base,
unsigned char device,
unsigned char address)
static inline unsigned short do_smbus_read_word(unsigned smbus_io_base,
unsigned char device, unsigned char address)
{
unsigned short val = 0;
_doread(smbus_io_base, device, address, (unsigned char *)&val,
@ -304,15 +302,15 @@ static int _dowrite(unsigned smbus_io_base, unsigned char device,
return -1;
}
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned char device,
unsigned char address, unsigned char data)
static inline int do_smbus_write_byte(unsigned smbus_io_base,
unsigned char device, unsigned char address, unsigned char data)
{
return _dowrite(smbus_io_base, device, address,
(unsigned char *)&data, 1);
}
static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device,
unsigned char address, unsigned short data)
static inline int do_smbus_write_word(unsigned smbus_io_base,
unsigned char device, unsigned char address, unsigned short data)
{
return _dowrite(smbus_io_base, device, address, (unsigned char *)&data,
2);

9
src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
View File

@ -25,21 +25,22 @@ static void enable_smbus(void)
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
}
static int smbus_recv_byte(unsigned device)
static inline int smbus_recv_byte(unsigned device)
{
return do_smbus_recv_byte(SMBUS_IO_BASE, device);
}
static int smbus_send_byte(unsigned device, unsigned char val)
static inline int smbus_send_byte(unsigned device, unsigned char val)
{
return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
static int smbus_read_byte(unsigned device, unsigned address)
static inline int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}

9
src/southbridge/intel/esb6300/esb6300_smbus.c
View File

@ -8,13 +8,10 @@
#include "esb6300.h"
#include "esb6300_smbus.h"
static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
static int lsmbus_read_byte(device_t dev, uint8_t address)
{
unsigned device;
struct resource *res;
device = dev->path.i2c.device;
res = find_resource(bus->dev, 0x20);
res = find_resource(dev, 0x20);
return do_smbus_read_byte(res->base, device, address);
}
@ -22,10 +19,12 @@ static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
};
static struct pci_operations lops_pci = {
/* The subsystem id follows the ide controller */
.set_subsystem = 0,
};
static struct device_operations smbus_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,

14
src/southbridge/intel/esb6300/esb6300_smbus.h
View File

@ -14,18 +14,12 @@
#define SMBUS_TIMEOUT (100*1000*10)
static void smbus_delay(void)
{
outb(0x80, 0x80);
}
static int smbus_wait_until_ready(unsigned smbus_io_base)
{
unsigned loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
udelay(100);
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
@ -38,7 +32,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
unsigned loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
udelay(100);
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
@ -46,18 +40,20 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
return loops?0:-1;
}
#ifdef UNUSED_CODE
static int smbus_wait_until_blk_done(unsigned smbus_io_base)
{
unsigned loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
udelay(100);
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
} while((byte&(1<<7)) == 0);
return loops?0:-1;
}
#endif
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
{

4
src/southbridge/intel/i82801cx/i82801cx.h
View File

@ -2,8 +2,10 @@
#define I82801CX_H
#if !defined(__PRE_RAM__)
#include <device/device.h>
#include "chip.h"
extern void i82801cx_enable(device_t dev);
void i82801cx_enable(device_t dev);
void i82801cx_hard_reset(void);
#endif

1
src/southbridge/intel/i82801cx/i82801cx_reset.c
View File

@ -1,4 +1,5 @@
#include <arch/io.h>
#include "i82801cx.h"
void i82801cx_hard_reset(void)
{

3
src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
View File

@ -134,6 +134,9 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned
}
#include "src/pc80/udelay_io.c"
#include "src/lib/delay.c"
static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
{
uint32_t tgio_ctrl;