Fix files with multiple newlines at the end.
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -28,4 +28,3 @@
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# Exclude the vendorcode directory
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--exclude src/vendorcode
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@ -63,4 +63,3 @@ unsigned long write_pirq_routing_table(unsigned long start);
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void pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]);
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#endif /* ARCH_PIRQ_ROUTING_H */
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@ -75,4 +75,3 @@ void agesa_postcar(struct sysinfo *cb)
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post_code(0x62);
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}
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}
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@ -70,4 +70,3 @@ consistent with the licensing of the Independent Modules.
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The availability of this Exception does not imply any general
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presumption that third-party software is unaffected by the copyleft
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requirements of the license of GCC.
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@ -1,3 +1,2 @@
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ramstage-y += cstates.c
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romstage-y += gpio.c
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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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// Instantiate all solution relevant data.
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#include "PlatformInstall.h"
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@ -29,4 +29,3 @@ void variant_nhlt_oem_overrides(const char **oem_id,
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*oem_table_id = CONFIG_VARIANT_DIR;
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*oem_revision = variant_board_sku();
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}
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@ -218,4 +218,3 @@ static const struct pad_config early_gpio_table[] = {
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#endif
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#endif
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@ -1,3 +1,2 @@
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config BOARD_INTEL_LEAFHILL
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bool "Leafhill"
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@ -348,4 +348,3 @@ const struct pad_config *sleep_gpio_table(size_t *num)
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*num = ARRAY_SIZE(sleep_gpio_table_config);
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return sleep_gpio_table_config;
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}
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@ -34,4 +34,3 @@ struct chip_operations mainboard_ops = {
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void h8_mainboard_init_dock (void)
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{
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}
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@ -231,5 +231,3 @@ const char *smbios_mainboard_sku(void)
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -18,4 +18,3 @@ romstage-y += pei_data.c
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ramstage-y += pei_data.c
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ramstage-y += ramstage.c
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ramstage-y += hda_verb.c
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@ -89,4 +89,3 @@ void soc_xdci_init(struct device *dev)
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{
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configure_host_mode_port0(dev);
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}
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@ -25,4 +25,3 @@ void bootblock_cpu_init(void)
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IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
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fast_spi_cache_bios_region();
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}
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@ -249,4 +249,3 @@
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#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)
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#endif
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@ -29,4 +29,3 @@ struct chipset_power_state *fill_power_state(void)
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return ps;
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}
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@ -4,4 +4,3 @@ config SOC_INTEL_COMMON_BLOCK_CSE
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help
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Driver for communication with Converged Security Engine (CSE)
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over Host Embedded Controller Interface (HECI)
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@ -133,4 +133,3 @@
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#define SGX_SUPPORTED (1<<2)
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#endif /* SOC_INTEL_COMMON_MSR_H */
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@ -19,4 +19,3 @@
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void soc_xhci_init(struct device *dev);
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#endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */
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@ -2,4 +2,3 @@ config SOC_INTEL_COMMON_BLOCK_SATA
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bool
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help
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Intel Processor common SATA support
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@ -6,4 +6,3 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c
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