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soc/amd/common/block/acpimmio: add remote GPIO bank ACPIMMIO region 

Currently coreboot for the AMD SOCs only supports accessing the up to 4
main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne
have another GPIO bank in the ACPIMMIO region that can contain up to 48
GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The
first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers
and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO
MUX registers.

BUG=b:194524995

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Felix Held 2021-07-28 14:08:07 +02:00
parent 7bbde76014
commit 467eb569c0
3 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/amd/common/block/acpimmio/mmio_util.c
View File

@ -34,6 +34,7 @@ DECLARE_ACPIMMIO(acpimmio_asf, ASF);
DECLARE_ACPIMMIO(acpimmio_smbus, SMBUS); DECLARE_ACPIMMIO(acpimmio_smbus, SMBUS);
DECLARE_ACPIMMIO(acpimmio_wdt, WDT); DECLARE_ACPIMMIO(acpimmio_wdt, WDT);
DECLARE_ACPIMMIO(acpimmio_hpet, HPET); DECLARE_ACPIMMIO(acpimmio_hpet, HPET);
DECLARE_ACPIMMIO(acpimmio_remote_gpio, REMOTE_GPIO);
DECLARE_ACPIMMIO(acpimmio_dpvga, DPVGA); DECLARE_ACPIMMIO(acpimmio_dpvga, DPVGA);
DECLARE_ACPIMMIO(acpimmio_xhci_pm, XHCIPM); DECLARE_ACPIMMIO(acpimmio_xhci_pm, XHCIPM);
DECLARE_ACPIMMIO(acpimmio_acdc_tmr, ACDCTMR); DECLARE_ACPIMMIO(acpimmio_acdc_tmr, ACDCTMR);

1
src/soc/amd/common/block/include/amdblocks/acpimmio.h
View File

@ -70,6 +70,7 @@ extern uint8_t *MAYBE_CONST acpimmio_wdt;
extern uint8_t *MAYBE_CONST acpimmio_hpet; extern uint8_t *MAYBE_CONST acpimmio_hpet;
extern uint8_t *MAYBE_CONST acpimmio_iomux; extern uint8_t *MAYBE_CONST acpimmio_iomux;
extern uint8_t *MAYBE_CONST acpimmio_misc; extern uint8_t *MAYBE_CONST acpimmio_misc;
extern uint8_t *MAYBE_CONST acpimmio_remote_gpio;
extern uint8_t *MAYBE_CONST acpimmio_dpvga; extern uint8_t *MAYBE_CONST acpimmio_dpvga;
extern uint8_t *MAYBE_CONST acpimmio_gpio0; extern uint8_t *MAYBE_CONST acpimmio_gpio0;
extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; extern uint8_t *MAYBE_CONST acpimmio_xhci_pm;

4
src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
View File

@ -62,6 +62,9 @@
* +---------------------------------------------------------------------------+ * +---------------------------------------------------------------------------+
* |0x1000 Serial debug bus | * |0x1000 Serial debug bus |
* +---------------------------------------------------------------------------+ * +---------------------------------------------------------------------------+
* |0x1200 remote GPIO configuration registers |
* | * contains both GPIO and MUX registers |
* +---------------------------------------------------------------------------+
* |0x1400 DP-VGA | * |0x1400 DP-VGA |
* +---------------------------------------------------------------------------+ * +---------------------------------------------------------------------------+
* |0x1500 GPIO configuration registers bank 0 | * |0x1500 GPIO configuration registers bank 0 |
@ -117,6 +120,7 @@
#define ACPIMMIO_HPET_BANK 0x0c00 #define ACPIMMIO_HPET_BANK 0x0c00
#define ACPIMMIO_IOMUX_BANK 0x0d00 #define ACPIMMIO_IOMUX_BANK 0x0d00
#define ACPIMMIO_MISC_BANK 0x0e00 #define ACPIMMIO_MISC_BANK 0x0e00
#define ACPIMMIO_REMOTE_GPIO_BANK 0x1200
#define ACPIMMIO_DPVGA_BANK 0x1400 #define ACPIMMIO_DPVGA_BANK 0x1400
#define ACPIMMIO_GPIO0_BANK 0x1500 #define ACPIMMIO_GPIO0_BANK 0x1500
#define ACPIMMIO_XHCIPM_BANK 0x1c00 #define ACPIMMIO_XHCIPM_BANK 0x1c00