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haswell/lynxpoint: Use new PCH/PM helper functions 

This makes use of the new functions from pmutil.c that take
care of the differences between -H and -LP chipsets.

It also adds support for the LynxPoint-LP GPE0 register block
and the SMI/SCI routing differences.

The FADT is updated to report the new 256 byte GPE0 block on
wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address
block so that part is zeroed to prevent IASL and the kernel
from complaining about a mismatch.

This was tested on WTM2.  Unfortunately I am still unable to get an
SCI delivered from the EC but I suspect that is due to a magic
command needed to put the EC in ACPI mode.  Instead I verified that
all of the power management and GPIO registers were set to expected
values.

I also tested transitions into S3 and S5 from both the kernel and
by pressing the power button at the developer mode screen and they
all function as expected.

Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2816
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie 2013-03-08 17:00:37 -08:00 committed by Ronald G. Minnich
parent 7922b468b5
commit 467f31de92
10 changed files with 111 additions and 509 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/baskingridge/devicetree.cb
View File

@ -48,7 +48,7 @@ chip northbridge/intel/haswell
register "gpi1_routing" = "1"
register "gpi14_routing" = "2"
register "alt_gp_smi_en" = "0x0000"
register "gpe0_en" = "0x4000"
register "gpe0_en_1" = "0x4000"
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"

9
src/mainboard/intel/wtm1/devicetree.cb
View File

@ -41,12 +41,11 @@ chip northbridge/intel/haswell
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpe0_en" = "0x0000"
register "gpe0_en_1" = "0x00000000"
register "gpe0_en_2" = "0x00000000"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"

14
src/mainboard/intel/wtm1/fadt.c
View File

@ -21,12 +21,12 @@
#include <device/pci.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/lynxpoint/pch.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
0x40) & 0xfffe;
u16 pmbase = get_pmbase();
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
@ -55,14 +55,14 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = pmbase + 0x50;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x20;
fadt->gpe0_blk = pmbase + 0x80;
fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
fadt->gpe0_blk_len = 32;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
@ -137,11 +137,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 64;
fadt->x_gpe0_blk.space_id = 0;
fadt->x_gpe0_blk.bit_width = 0;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pmbase + 0x20;
fadt->x_gpe0_blk.addrl = 0;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;

9
src/mainboard/intel/wtm2/devicetree.cb
View File

@ -41,12 +41,11 @@ chip northbridge/intel/haswell
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpe0_en" = "0x0000"
register "gpe0_en_1" = "0x00000400"
register "gpe0_en_2" = "0x00000000"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"

14
src/mainboard/intel/wtm2/fadt.c
View File

@ -21,12 +21,12 @@
#include <device/pci.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/lynxpoint/pch.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
0x40) & 0xfffe;
u16 pmbase = get_pmbase();
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
@ -55,14 +55,14 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = pmbase + 0x50;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x20;
fadt->gpe0_blk = pmbase + 0x80;
fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
fadt->gpe0_blk_len = 32;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
@ -137,11 +137,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 64;
fadt->x_gpe0_blk.space_id = 0;
fadt->x_gpe0_blk.bit_width = 0;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pmbase + 0x20;
fadt->x_gpe0_blk.addrl = 0;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;

13
src/northbridge/intel/haswell/acpi.c
View File

@ -182,17 +182,12 @@ int init_igd_opregion(igd_opregion_t *opregion)
pci_write_config16(igd, SWSCI, reg16);
/* clear dmisci status */
reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
reg16 = inw(get_pmbase() + TCO1_STS);
reg16 |= DMISCI_STS; // reference code does an &=
outw(DEFAULT_PMBASE + TCO1_STS, reg16);
outw(get_pmbase() + TCO1_STS, reg16);
/* clear acpi tco status */
outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
/* enable acpi tco scis */
reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
reg16 |= TCOSCI_EN;
outw(DEFAULT_PMBASE + GPE0_EN, reg16);
/* clear and enable ACPI TCO SCI */
enable_tco_sci();
return 0;
}

9
src/southbridge/intel/lynxpoint/chip.h
View File

@ -35,7 +35,7 @@ struct southbridge_intel_lynxpoint_config {
uint8_t pirqh_routing;
/**
* GPI Routing configuration
* GPI Routing configuration for LynxPoint-H
*
* Only the lower two bits have a meaning:
* 00: No effect
@ -60,8 +60,11 @@ struct southbridge_intel_lynxpoint_config {
uint8_t gpi14_routing;
uint8_t gpi15_routing;
uint32_t gpe0_en;
uint16_t alt_gp_smi_en;
uint32_t gpe0_en_1;
uint32_t gpe0_en_2;
uint32_t gpe0_en_3;
uint32_t gpe0_en_4;
uint32_t alt_gp_smi_en;
/* IDE configuration */
uint32_t ide_legacy_combined;

21
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -184,12 +185,12 @@ static void pch_gpi_routing(device_t dev)
static void pch_power_options(device_t dev)
{
u8 reg8;
u16 reg16, pmbase;
u16 reg16;
u32 reg32;
const char *state;
/* Get the chip configuration */
config_t *config = dev->chip_info;
u16 pmbase = get_pmbase();
int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
int nmi_option;
@ -257,13 +258,19 @@ static void pch_power_options(device_t dev)
reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME
pci_write_config16(dev, GEN_PMCON_1, reg16);
// Set the board's GPI routing.
pch_gpi_routing(dev);
/*
* Set the board's GPI routing on LynxPoint-H.
* This is done as part of GPIO configuration on LynxPoint-LP.
*/
if (pch_is_lp())
pch_gpi_routing(dev);
pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
/* GPE setup based on device tree configuration */
enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
config->gpe0_en_3, config->gpe0_en_4);
outl(config->gpe0_en, pmbase + GPE0_EN);
outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
/* SMI setup based on device tree configuration */
enable_alt_smi(config->alt_gp_smi_en);
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); // PM1_CNT

250
src/southbridge/intel/lynxpoint/smi.c
View File

@ -30,240 +30,34 @@
#include <string.h>
#include "pch.h"
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
*/
static u16 pmbase = DEFAULT_PMBASE;
/**
* @brief read and clear PM1_STS
* @return PM1_STS register
*/
static u16 reset_pm1_status(void)
{
u16 reg16;
reg16 = inw(pmbase + PM1_STS);
/* set status bits are cleared by writing 1 to them */
outw(reg16, pmbase + PM1_STS);
return reg16;
}
static void dump_pm1_status(u16 pm1_sts)
{
printk(BIOS_DEBUG, "PM1_STS: ");
if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
printk(BIOS_DEBUG, "\n");
}
/**
* @brief read and clear SMI_STS
* @return SMI_STS register
*/
static u32 reset_smi_status(void)
{
u32 reg32;
reg32 = inl(pmbase + SMI_STS);
/* set status bits are cleared by writing 1 to them */
outl(reg32, pmbase + SMI_STS);
return reg32;
}
static void dump_smi_status(u32 smi_sts)
{
printk(BIOS_DEBUG, "SMI_STS: ");
if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
printk(BIOS_DEBUG, "\n");
}
/**
* @brief read and clear GPE0_STS
* @return GPE0_STS register
*/
static u32 reset_gpe0_status(void)
{
u32 reg32;
reg32 = inl(pmbase + GPE0_STS);
/* set status bits are cleared by writing 1 to them */
outl(reg32, pmbase + GPE0_STS);
return reg32;
}
static void dump_gpe0_status(u32 gpe0_sts)
{
int i;
printk(BIOS_DEBUG, "GPE0_STS: ");
for (i=31; i<= 16; i--) {
if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
}
if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
printk(BIOS_DEBUG, "\n");
}
/**
* @brief read and clear ALT_GP_SMI_STS
* @return ALT_GP_SMI_STS register
*/
static u16 reset_alt_gp_smi_status(void)
{
u16 reg16;
reg16 = inl(pmbase + ALT_GP_SMI_STS);
/* set status bits are cleared by writing 1 to them */
outl(reg16, pmbase + ALT_GP_SMI_STS);
return reg16;
}
static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
{
int i;
printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
for (i=15; i<= 0; i--) {
if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16));
}
printk(BIOS_DEBUG, "\n");
}
/**
* @brief read and clear TCOx_STS
* @return TCOx_STS registers
*/
static u32 reset_tco_status(void)
{
u32 tcobase = pmbase + 0x60;
u32 reg32;
reg32 = inl(tcobase + 0x04);
/* set status bits are cleared by writing 1 to them */
outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
if (reg32 & (1 << 18))
outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
return reg32;
}
static void dump_tco_status(u32 tco_sts)
{
printk(BIOS_DEBUG, "TCO_STS: ");
if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
printk(BIOS_DEBUG, "\n");
}
/**
* @brief Set the EOS bit
*/
static void smi_set_eos(void)
{
u8 reg8;
reg8 = inb(pmbase + SMI_EN);
reg8 |= EOS;
outb(reg8, pmbase + SMI_EN);
}
void southbridge_smm_init(void)
{
u32 smi_en;
u16 pm1_en;
u32 gpe0_en;
#if CONFIG_ELOG
/* Log events from chipset before clearing */
pch_log_state();
#endif
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
PMBASE) & 0xff80;
printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
smi_en = inl(pmbase + SMI_EN);
smi_en = inl(get_pmbase() + SMI_EN);
if (smi_en & APMC_EN) {
printk(BIOS_INFO, "SMI# handler already enabled?\n");
return;
}
printk(BIOS_DEBUG, "\n");
dump_smi_status(reset_smi_status());
dump_pm1_status(reset_pm1_status());
dump_gpe0_status(reset_gpe0_status());
dump_alt_gp_smi_status(reset_alt_gp_smi_status());
dump_tco_status(reset_tco_status());
/* Disable GPE0 PME_B0 */
gpe0_en = inl(pmbase + GPE0_EN);
gpe0_en &= ~PME_B0_EN;
outl(gpe0_en, pmbase + GPE0_EN);
/* Dump and clear status registers */
clear_smi_status();
clear_pm1_status();
clear_tco_status();
clear_gpe_status();
pm1_en = 0;
pm1_en |= PWRBTN_EN;
pm1_en |= GBL_EN;
outw(pm1_en, pmbase + PM1_EN);
/* Configure events */
enable_pm1(PWRBTN_EN | GBL_EN);
disable_gpe(PME_B0_EN);
/* Enable SMI generation:
* - on TCO events
@ -273,23 +67,7 @@ void southbridge_smm_init(void)
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
*/
smi_en = 0; /* reset SMI enables */
#if 0
smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
#endif
smi_en |= TCO_EN;
smi_en |= APMC_EN;
smi_en |= SLP_SMI_EN;
#if 0
smi_en |= BIOS_EN;
#endif
/* The following need to be on for SMIs to happen */
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
enable_smi(TCO_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void southbridge_trigger_smi(void)
@ -315,13 +93,13 @@ void southbridge_trigger_smi(void)
void southbridge_clear_smi_status(void)
{
/* Clear SMI status */
reset_smi_status();
clear_smi_status();
/* Clear PM1 status */
reset_pm1_status();
clear_pm1_status();
/* Set EOS bit so other SMIs can occur. */
smi_set_eos();
enable_smi(EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)

279
src/southbridge/intel/lynxpoint/smihandler.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -33,14 +34,6 @@
#include "nvs.h"
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
*/
static u16 pmbase = DEFAULT_PMBASE;
u16 smm_get_pmbase(void)
{
return pmbase;
}
static u8 smm_initialized = 0;
@ -53,157 +46,6 @@ global_nvs_t *smm_get_gnvs(void)
return gnvs;
}
/**
* @brief read and clear PM1_STS
* @return PM1_STS register
*/
static u16 reset_pm1_status(void)
{
u16 reg16;
reg16 = inw(pmbase + PM1_STS);
/* set status bits are cleared by writing 1 to them */
outw(reg16, pmbase + PM1_STS);
return reg16;
}
static void dump_pm1_status(u16 pm1_sts)
{
printk(BIOS_SPEW, "PM1_STS: ");
if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
printk(BIOS_SPEW, "\n");
int reg16 = inw(pmbase + PM1_EN);
printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
}
/**
* @brief read and clear SMI_STS
* @return SMI_STS register
*/
static u32 reset_smi_status(void)
{
u32 reg32;
reg32 = inl(pmbase + SMI_STS);
/* set status bits are cleared by writing 1 to them */
outl(reg32, pmbase + SMI_STS);
return reg32;
}
static void dump_smi_status(u32 smi_sts)
{
printk(BIOS_DEBUG, "SMI_STS: ");
if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
printk(BIOS_DEBUG, "\n");
}
/**
* @brief read and clear GPE0_STS
* @return GPE0_STS register
*/
static u32 reset_gpe0_status(void)
{
u32 reg32;
reg32 = inl(pmbase + GPE0_STS);
/* set status bits are cleared by writing 1 to them */
outl(reg32, pmbase + GPE0_STS);
return reg32;
}
static void dump_gpe0_status(u32 gpe0_sts)
{
int i;
printk(BIOS_DEBUG, "GPE0_STS: ");
for (i=31; i<= 16; i--) {
if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
}
if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW ");
if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");
if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG ");
if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
printk(BIOS_DEBUG, "\n");
}
/**
* @brief read and clear TCOx_STS
* @return TCOx_STS registers
*/
static u32 reset_tco_status(void)
{
u32 tcobase = pmbase + 0x60;
u32 reg32;
reg32 = inl(tcobase + 0x04);
/* set status bits are cleared by writing 1 to them */
outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
if (reg32 & (1 << 18))
outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
return reg32;
}
static void dump_tco_status(u32 tco_sts)
{
printk(BIOS_DEBUG, "TCO_STS: ");
if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
printk(BIOS_DEBUG, "\n");
}
int southbridge_io_trap_handler(int smif)
{
switch (smif) {
@ -226,11 +68,7 @@ int southbridge_io_trap_handler(int smif)
*/
void southbridge_smi_set_eos(void)
{
u8 reg8;
reg8 = inb(pmbase + SMI_EN);
reg8 |= EOS;
outb(reg8, pmbase + SMI_EN);
enable_smi(EOS);
}
static void busmaster_disable_on_bus(int bus)
@ -274,6 +112,7 @@ static void southbridge_smi_sleep(void)
u32 reg32;
u8 slp_typ;
u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
u16 pmbase = get_pmbase();
// save and recover RTC port values
u8 tmp70, tmp72;
@ -284,9 +123,7 @@ static void southbridge_smi_sleep(void)
outb(tmp72, 0x72);
/* First, disable further SMIs */
reg8 = inb(pmbase + SMI_EN);
reg8 &= ~SLP_SMI_EN;
outb(reg8, pmbase + SMI_EN);
disable_smi(SLP_SMI_EN);
/* Figure out SLP_TYP */
reg32 = inl(pmbase + PM1_CNT);
@ -306,19 +143,26 @@ static void southbridge_smi_sleep(void)
*/
switch (slp_typ) {
case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
case 5:
case SLP_TYP_S0:
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
break;
case SLP_TYP_S1:
printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
break;
case SLP_TYP_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */
wbinvd();
break;
case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
case 7:
case SLP_TYP_S4:
printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
break;
case SLP_TYP_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
outl(0, pmbase + GPE0_EN);
/* Disable all GPE */
disable_all_gpe();
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
@ -334,14 +178,16 @@ static void southbridge_smi_sleep(void)
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
break;
default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
default:
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
break;
}
/* Write back to the SLP register to cause the originally intended
* event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
outl(reg32 | SLP_EN, pmbase + PM1_CNT);
enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
@ -354,8 +200,7 @@ static void southbridge_smi_sleep(void)
reg32 = inl(pmbase + PM1_CNT);
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
reg32 &= ~(SLP_EN | SLP_TYP);
outl(reg32, pmbase + PM1_CNT);
disable_pm1_control(SLP_EN | SLP_TYP);
}
}
@ -420,7 +265,6 @@ static void southbridge_smi_gsmi(void)
static void southbridge_smi_apmc(void)
{
u32 pmctrl;
u8 reg8;
em64t101_smm_state_save_area_t *state;
@ -443,20 +287,17 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "P-state control\n");
break;
case APM_CNT_ACPI_DISABLE:
pmctrl = inl(pmbase + PM1_CNT);
pmctrl &= ~SCI_EN;
outl(pmctrl, pmbase + PM1_CNT);
disable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
pmctrl = inl(pmbase + PM1_CNT);
pmctrl |= SCI_EN;
outl(pmctrl, pmbase + PM1_CNT);
enable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_GNVS_UPDATE:
if (smm_initialized) {
printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
printk(BIOS_DEBUG,
"SMI#: SMM structures already initialized!\n");
return;
}
state = smi_apmc_find_state_save(reg8);
@ -479,53 +320,41 @@ static void southbridge_smi_apmc(void)
static void southbridge_smi_pm1(void)
{
u16 pm1_sts;
pm1_sts = reset_pm1_status();
dump_pm1_status(pm1_sts);
u16 pm1_sts = clear_pm1_status();
/* While OSPM is not active, poweroff immediately
* on a power button event.
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
#if CONFIG_ELOG_GSMI
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);
disable_pm1_control(-1UL);
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
}
}
static void southbridge_smi_gpe0(void)
{
u32 gpe0_sts;
gpe0_sts = reset_gpe0_status();
dump_gpe0_status(gpe0_sts);
clear_gpe_status();
}
static void southbridge_smi_gpi(void)
{
u16 reg16;
reg16 = inw(pmbase + ALT_GP_SMI_STS);
outw(reg16, pmbase + ALT_GP_SMI_STS);
mainboard_smi_gpi(clear_alt_smi_status());
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
mainboard_smi_gpi(reg16);
outw(reg16, pmbase + ALT_GP_SMI_STS);
/* Clear again after mainboard handler */
clear_alt_smi_status();
}
static void southbridge_smi_mc(void)
{
u32 reg32;
reg32 = inl(pmbase + SMI_EN);
reg32 = inl(get_pmbase() + SMI_EN);
/* Are periodic SMIs enabled? */
/* Are microcontroller SMIs enabled? */
if ((reg32 & MCSMI_EN) == 0)
return;
@ -536,9 +365,7 @@ static void southbridge_smi_mc(void)
static void southbridge_smi_tco(void)
{
u32 tco_sts;
tco_sts = reset_tco_status();
u32 tco_sts = clear_tco_status();
/* Any TCO event? */
if (!tco_sts)
@ -561,13 +388,12 @@ static void southbridge_smi_tco(void)
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc,
(bios_cntl & ~1));
} /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */
printk(BIOS_DEBUG, "TCO Timeout.\n");
} else if (!tco_sts) {
dump_tco_status(tco_sts);
}
}
@ -575,7 +401,7 @@ static void southbridge_smi_periodic(void)
{
u32 reg32;
reg32 = inl(pmbase + SMI_EN);
reg32 = inl(get_pmbase() + SMI_EN);
/* Are periodic SMIs enabled? */
if ((reg32 & PERIODIC_EN) == 0)
@ -624,11 +450,14 @@ static void southbridge_smi_monitor(void)
// Fall through to debug
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
trap_cycle & 0xfffc);
for (i=0; i < 4; i++)
if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
printk(BIOS_DEBUG, " read/write: %s\n",
(trap_cycle & (1 << 24)) ? "read" : "write");
if (!(trap_cycle & (1 << 24))) {
/* Write Cycle */
@ -683,16 +512,13 @@ static smi_handler_t southbridge_smi[32] = {
void southbridge_smi_handler(void)
{
int i, dump = 0;
int i;
u32 smi_sts;
/* Update global variable pmbase */
pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
smi_sts = reset_smi_status();
smi_sts = clear_smi_status();
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < 31; i++) {
@ -700,15 +526,10 @@ void southbridge_smi_handler(void)
if (southbridge_smi[i]) {
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
"handler available.\n", i);
dump = 1;
printk(BIOS_DEBUG,
"SMI_STS[%d] occured, but no "
"handler available.\n", i);
}
}
}
if(dump) {
dump_smi_status(smi_sts);
}
}