mainboard/aopen: Use C89 comments style & remove commented code
Change-Id: I0014fc030888d71f7951c97bccc7cef0e1c45186 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16922 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
Martin Roth
parent
626f8c8440
commit
46829869c8
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@ -32,37 +32,37 @@ unsigned long acpi_fill_madt(unsigned long current)
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device_t dev = 0;
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struct resource* res = NULL;
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// SJM: Hard-code CPU LAPIC entries for now
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/* SJM: Hard-code CPU LAPIC entries for now */
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
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// Southbridge IOAPIC
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/* Southbridge IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start);
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irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
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// P64H2 Bus B IOAPIC
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/* P64H2 Bus B IOAPIC */
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dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
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if (!dev)
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BUG(); // Config.lb error?
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BUG(); /* Config.lb error? */
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start);
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irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
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// P64H2 Bus A IOAPIC
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/* P64H2 Bus A IOAPIC */
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dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
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if (!dev)
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BUG(); // Config.lb error?
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BUG(); /* Config.lb error? */
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start);
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irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
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// Map ISA IRQ 0 to IRQ 2
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/* Map ISA IRQ 0 to IRQ 2 */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
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// IRQ9 differs from ISA standard - ours is active high, level-triggered
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/* IRQ9 differs from ISA standard - ours is active high, level-triggered */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
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return current;
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@ -16,23 +16,24 @@
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#ifndef DXPLPLUSU_BUS_H_INCLUDED
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#define DXPLPLUSU_BUS_H_INCLUDED
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// These were determined by seeing how coreboot enumerates the various
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// PCI (and PCI-like) buses on the board.
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/* These were determined by seeing how coreboot enumerates the various
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* PCI (and PCI-like) buses on the board.
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*/
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#define PCI_BUS_ROOT 0
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#define PCI_BUS_AGP 1 // AGP
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#define PCI_BUS_E7501_HI_B 2 // P64H2#1
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#define PCI_BUS_P64H2_B 3 // P64H2#1 bus B
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#define PCI_BUS_P64H2_A 4 // P64H2#1 bus A
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#define PCI_BUS_ICH4 5 // ICH4
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#define PCI_BUS_AGP 1 /* AGP */
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#define PCI_BUS_E7501_HI_B 2 /* P64H2#1 */
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#define PCI_BUS_P64H2_B 3 /* P64H2#1 bus B */
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#define PCI_BUS_P64H2_A 4 /* P64H2#1 bus A */
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#define PCI_BUS_ICH4 5 /* ICH4 */
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// IOAPIC addresses determined by coreboot enumeration.
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// Someday add functions to get APIC IDs and versions from the chips themselves.
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/* IOAPIC addresses determined by coreboot enumeration. */
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/* Someday add functions to get APIC IDs and versions from the chips themselves. */
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#define IOAPIC_ICH4 2
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#define IOAPIC_P64H2_BUS_B 3 // IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010
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#define IOAPIC_P64H2_BUS_A 4 // IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010
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#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 */
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#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 */
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#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-4 and P64-H2
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#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */
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#endif
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@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
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/* XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) */
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fadt->pm2_cnt_len = 0;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 8;
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@ -31,37 +31,37 @@
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static const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE,
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PIRQ_VERSION,
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32 + 16 * CONFIG_IRQ_SLOT_COUNT, // Size of this struct in bytes
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0, // PCI bus number on which the interrupt router resides
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PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router
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0, // PCI-exclusive IRQ bitmap
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PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router
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PCI_DEVICE_ID_INTEL_82801DB_LPC, // Device ID of compatible PCI interrupt router
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0, // Additional miniport information
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero
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0xB1, // Checksum of the entire structure (causes 8-bit sum == 0)
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32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Size of this struct in bytes */
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0, /* PCI bus number on which the interrupt router resides */
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PCI_DEVFN(31, 0), /* PCI device/function number of the interrupt router */
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0, /* PCI-exclusive IRQ bitmap */
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PCI_VENDOR_ID_INTEL, /* Vendor ID of compatible PCI interrupt router */
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PCI_DEVICE_ID_INTEL_82801DB_LPC, /* Device ID of compatible PCI interrupt router */
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0, /* Additional miniport information */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* Reserved, must be zero */
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0xB1, /* Checksum of the entire structure (causes 8-bit sum == 0) */
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{
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// NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
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// This was determined from linux-2.6.11/arch/i386/pci/irq.c
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// bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
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// ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
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// Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
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/* NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space */
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/* This was determined from linux-2.6.11/arch/i386/pci/irq.c */
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/* bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 */
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/* ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 */
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/* Not sure why IRQ9 isn't routable (inherited from Tyan S2735) */
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// INTA# INTB# INTC# INTD#
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// bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
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/* INTA# INTB# INTC# INTD# */
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/* bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu */
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{PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus
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{PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // USB 1.1
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{PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, /* IDE / SMBus */
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{PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* USB 1.1 */
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{PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
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{PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
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{PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // GbE
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{PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* GbE */
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{PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
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{PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
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{PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // SCSI
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{PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* SCSI */
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{PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // 32-bit slot
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{PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* 32-bit slot */
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}
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};
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@ -46,14 +46,14 @@ void mainboard_romstage_entry(unsigned long bist)
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},
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};
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// Get the serial port running and print a welcome banner
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/* Get the serial port running and print a welcome banner */
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lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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// Halt if there was a built in self test failure
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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// If this is a warm boot, some initialization can be skipped
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/* If this is a warm boot, some initialization can be skipped */
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if (!e7505_mch_is_ready()) {
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enable_smbus();
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