src/[northbridge,security]: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If6b5930f78c3da6dcefaa7b6202cd0424a24525b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Martin Roth
Martin Roth
parent
36fcc85be4
commit
468d02cc82
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@ -645,7 +645,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
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if (base_k > 4 *1024 * 1024) break; // don't need to go to check
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if (limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
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mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G
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mem_hole.node_id = i;
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break; //only one hole
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}
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@ -661,7 +661,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
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if (base_k > 4 *1024 * 1024) break; // don't need to go to check
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if (limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
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mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G
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mem_hole.node_id = i;
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break; //only one hole
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}
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@ -50,11 +50,11 @@ void enumerate_ht_chain(void)
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* non Coherent links the appropriate bus registers for the
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* links needs to be programed to point at bus 0.
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*/
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unsigned next_unitid, last_unitid = 0;
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unsigned int next_unitid, last_unitid = 0;
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#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
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// let't record the device of last ht device, So we can set the
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// Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
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unsigned real_last_unitid = 0;
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unsigned int real_last_unitid = 0;
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u8 real_last_pos = 0;
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int ht_dev_num = 0; // except host_bridge
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u8 end_used = 0;
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@ -96,8 +96,8 @@ void enumerate_ht_chain(void)
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pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags);
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flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
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if ((flags >> 13) == 0) {
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unsigned count;
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unsigned ctrl, ctrl_off;
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unsigned int count;
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unsigned int ctrl, ctrl_off;
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pci_devfn_t devx;
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#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
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@ -62,7 +62,7 @@ static struct device *__f0_dev[FX_DEVS];
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struct device *__f1_dev[FX_DEVS];
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static struct device *__f2_dev[FX_DEVS];
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static struct device *__f4_dev[FX_DEVS];
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static unsigned fx_devs = 0;
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static unsigned int fx_devs = 0;
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struct device *get_node_pci(u32 nodeid, u32 fn)
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{
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@ -94,14 +94,14 @@ static void get_fx_devs(void)
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}
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}
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static u32 f1_read_config32(unsigned reg)
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static u32 f1_read_config32(unsigned int reg)
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{
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if (fx_devs == 0)
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get_fx_devs();
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return pci_read_config32(__f1_dev[0], reg);
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}
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static void f1_write_config32(unsigned reg, u32 value)
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static void f1_write_config32(unsigned int reg, u32 value)
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{
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int i;
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if (fx_devs == 0)
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@ -118,7 +118,7 @@ static void f1_write_config32(unsigned reg, u32 value)
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u32 amdfam10_nodeid(struct device *dev)
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{
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#if NODE_NUMS == 64
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unsigned busn;
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unsigned int busn;
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busn = dev->bus->secondary;
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if (busn != CONFIG_CBB) {
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return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
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@ -361,11 +361,11 @@ static void amdfam10_scan_chains(struct device *dev)
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}
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static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
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unsigned goal_link)
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static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid,
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unsigned int goal_link)
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{
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struct resource *res;
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unsigned nodeid, link = 0;
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unsigned int nodeid, link = 0;
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int result;
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res = 0;
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for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
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@ -389,7 +389,7 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node
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return result;
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}
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static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
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static struct resource *amdfam10_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link)
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{
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struct resource *resource;
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u32 free_reg, reg;
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@ -514,7 +514,7 @@ static void amdfam10_set_resource(struct device *dev, struct resource *resource,
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u32 nodeid)
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{
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resource_t rbase, rend;
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unsigned reg, link_num;
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unsigned int reg, link_num;
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char buf[50];
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/* Make certain the resource has actually been set */
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@ -564,7 +564,7 @@ static void amdfam10_set_resource(struct device *dev, struct resource *resource,
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* but it is too difficult to deal with the resource allocation magic.
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*/
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static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid)
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static void amdfam10_create_vga_resource(struct device *dev, unsigned int nodeid)
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{
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struct bus *link;
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struct resource *res;
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@ -607,7 +607,7 @@ static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid)
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static void amdfam10_set_resources(struct device *dev)
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{
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unsigned nodeid;
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unsigned int nodeid;
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struct bus *bus;
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struct resource *res;
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@ -685,7 +685,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = {
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static void amdfam10_domain_read_resources(struct device *dev)
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{
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unsigned reg;
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unsigned int reg;
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uint8_t nvram;
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uint8_t enable_cc6;
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@ -697,7 +697,7 @@ static void amdfam10_domain_read_resources(struct device *dev)
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limit = f1_read_config32(reg + 0x04);
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/* Is this register allocated? */
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if ((base & 3) != 0) {
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unsigned nodeid, reg_link;
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unsigned int nodeid, reg_link;
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struct device *reg_dev;
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if (reg < 0xc0) { // mmio
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nodeid = (limit & 0xf) + (base&0x30);
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@ -817,7 +817,7 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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struct hw_mem_hole_info {
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unsigned hole_startk;
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unsigned int hole_startk;
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int node_id;
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};
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@ -857,7 +857,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
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if (base_k > 4 *1024 * 1024) break; // don't need to go to check
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if (limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
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mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G
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mem_hole.node_id = i;
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break; //only one hole
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}
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@ -949,7 +949,7 @@ static void amdfam10_domain_set_resources(struct device *dev)
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/* split the region to accommodate pci memory space */
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if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
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if (basek <= mmio_basek) {
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unsigned pre_sizek;
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unsigned int pre_sizek;
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pre_sizek = mmio_basek - basek;
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if (pre_sizek > 0) {
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ram_resource(dev, (idx | i), basek, pre_sizek);
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@ -1325,7 +1325,7 @@ static void sysconf_init(struct device *dev) // first node
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sysconf.segbit = 0;
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sysconf.ht_c_num = 0;
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unsigned ht_c_index;
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unsigned int ht_c_index;
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for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) {
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sysconf.ht_c_conf_bus[ht_c_index] = 0;
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@ -1386,12 +1386,12 @@ static void cpu_bus_scan(struct device *dev)
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int nvram = 0;
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int i,j;
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int nodes;
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unsigned nb_cfg_54;
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unsigned siblings;
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unsigned int nb_cfg_54;
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unsigned int siblings;
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int cores_found;
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int disable_siblings;
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uint8_t disable_cu_siblings = 0;
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unsigned ApicIdCoreIdSize;
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unsigned int ApicIdCoreIdSize;
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nb_cfg_54 = 0;
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ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
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@ -1485,7 +1485,7 @@ static void cpu_bus_scan(struct device *dev)
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for (i = 0; i < nodes; i++) {
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struct device *cdb_dev;
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unsigned busn, devn;
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unsigned int busn, devn;
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struct bus *pbus;
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uint8_t fam15h = 0;
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@ -26,6 +26,6 @@
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void set_bios_reset(void);
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void distinguish_cpu_resets(unsigned int nodeid);
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unsigned int get_sblk(void);
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unsigned int get_sbbusn(unsigned sblk);
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unsigned int get_sbbusn(unsigned int sblk);
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#endif /* AMDK8_H */
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@ -508,12 +508,12 @@ void K8FInterleaveBanks(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
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void mctInitWithWritetoCS(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
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void mctGet_PS_Cfg(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
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void Get_ChannelPS_Cfg0(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload,
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unsigned *AddrTmgCTL, unsigned *ODC_CTL);
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void Get_ChannelPS_Cfg1(unsigned MAAdimms, unsigned Speed, unsigned MAAload,
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unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val);
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void Get_ChannelPS_Cfg2(unsigned MAAdimms, unsigned Speed, unsigned MAAload,
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unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val);
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void Get_ChannelPS_Cfg0(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, unsigned int DATAAload,
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unsigned int *AddrTmgCTL, unsigned int *ODC_CTL);
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void Get_ChannelPS_Cfg1(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload,
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unsigned int *AddrTmgCTL, unsigned int *ODC_CTL, unsigned int *val);
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void Get_ChannelPS_Cfg2(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload,
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unsigned int *AddrTmgCTL, unsigned int *ODC_CTL, unsigned int *val);
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u8 MCTDefRet(void);
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@ -532,7 +532,7 @@ void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta
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void K8FCPUMemTyping_clear(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
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void K8FWaitMemClrDelay(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
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unsigned K8FCalcFinalDQSRcvValue(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, unsigned LeftRcvEn, unsigned RightRcvEn, unsigned *valid);
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unsigned int K8FCalcFinalDQSRcvValue(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, unsigned int LeftRcvEn, unsigned int RightRcvEn, unsigned int *valid);
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void K8FGetDeltaTSCPart1(struct DCTStatStruc *pDCTstat);
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void K8FGetDeltaTSCPart2(struct DCTStatStruc *pDCTstat);
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@ -314,7 +314,7 @@ static void read_resources(struct device *dev)
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static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
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{
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resource_t rbase, rend;
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unsigned reg, link_num;
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unsigned int reg, link_num;
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char buf[50];
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/* Make certain the resource has actually been set */
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@ -658,7 +658,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
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if (base_k > 4 *1024 * 1024) break; // don't need to go to check
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if (limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
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mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G
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mem_hole.node_id = i;
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break; //only one hole
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}
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@ -47,13 +47,13 @@ typedef struct dram_base_mask {
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u32 mask; //[47:27] at [28:8] and enable at bit 0
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} dram_base_mask_t;
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static unsigned node_nums;
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static unsigned sblink;
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static unsigned int node_nums;
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static unsigned int sblink;
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static struct device *__f0_dev[MAX_NODE_NUMS];
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static struct device *__f1_dev[MAX_NODE_NUMS];
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static struct device *__f2_dev[MAX_NODE_NUMS];
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static struct device *__f4_dev[MAX_NODE_NUMS];
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static unsigned fx_devs = 0;
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static unsigned int fx_devs = 0;
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static dram_base_mask_t get_dram_base_mask(u32 nodeid)
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{
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@ -122,14 +122,14 @@ static void get_fx_devs(void)
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printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
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}
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static u32 f1_read_config32(unsigned reg)
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static u32 f1_read_config32(unsigned int reg)
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{
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if (fx_devs == 0)
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get_fx_devs();
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return pci_read_config32(__f1_dev[0], reg);
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}
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static void f1_write_config32(unsigned reg, u32 value)
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static void f1_write_config32(unsigned int reg, u32 value)
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{
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int i;
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if (fx_devs == 0)
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@ -167,11 +167,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
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* @retval 0 resource exists, not usable
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* @retval 1 resource exist, resource has been allocated before
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*/
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static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
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unsigned goal_link)
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static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid,
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unsigned int goal_link)
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{
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struct resource *res;
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unsigned nodeid, link = 0;
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unsigned int nodeid, link = 0;
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int result;
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res = 0;
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for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
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@ -196,7 +196,7 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node
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return result;
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}
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static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
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static struct resource *amdfam15_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link)
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{
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struct resource *resource;
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u32 free_reg, reg;
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@ -301,7 +301,7 @@ static void read_resources(struct device *dev)
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static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
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{
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resource_t rbase, rend;
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unsigned reg, link_num;
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unsigned int reg, link_num;
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char buf[50];
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/* Make certain the resource has actually been set */
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@ -347,7 +347,7 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node
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* but it is too difficult to deal with the resource allocation magic.
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*/
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static void create_vga_resource(struct device *dev, unsigned nodeid)
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static void create_vga_resource(struct device *dev, unsigned int nodeid)
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{
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struct bus *link;
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@ -377,7 +377,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid)
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static void set_resources(struct device *dev)
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{
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unsigned nodeid;
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unsigned int nodeid;
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struct bus *bus;
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struct resource *res;
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@ -658,7 +658,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
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if (base_k > 4 *1024 * 1024) break; // don't need to go to check
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if (limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
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mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G
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mem_hole.node_id = i;
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break; //only one hole
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}
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@ -791,8 +791,8 @@ static void cpu_bus_scan(struct device *dev)
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int i,j;
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int coreid_bits;
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int core_max = 0;
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unsigned ApicIdCoreIdSize;
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unsigned core_nums;
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unsigned int ApicIdCoreIdSize;
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unsigned int core_nums;
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int siblings = 0;
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unsigned int family;
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u32 modules = 0;
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@ -830,7 +830,7 @@ static void cpu_bus_scan(struct device *dev)
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cpu_bus = dev->link_list;
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for (i = 0; i < node_nums; i++) {
|
||||
struct device *cdb_dev;
|
||||
unsigned devn;
|
||||
unsigned int devn;
|
||||
struct bus *pbus;
|
||||
|
||||
devn = DEV_CDB + i;
|
||||
|
|
|
|||
|
|
@ -882,7 +882,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
|
|||
base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
|
||||
if (base_k > 4 *1024 * 1024) break; // don't need to go to check
|
||||
if (limitk_pri != base_k) { // we find the hole
|
||||
mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
|
||||
mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G
|
||||
mem_hole.node_id = i;
|
||||
break; //only one hole
|
||||
}
|
||||
|
|
|
|||
|
|
@ -434,7 +434,7 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
|
|||
* @param dimm_socket_address SMBus address of DIMM socket to interrogate.
|
||||
* @return log2(number of bits) for each side of the DIMM.
|
||||
*/
|
||||
static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
|
||||
static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address)
|
||||
{
|
||||
int value;
|
||||
|
||||
|
|
@ -757,7 +757,7 @@ DIMM-independent configuration functions:
|
|||
* (0..MAX_DIMM_SOCKETS_PER_CHANNEL).
|
||||
* @return New multiple of 64 MB total DRAM in the system.
|
||||
*/
|
||||
static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index)
|
||||
static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned int dimm_index)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@ void get_gmch_info(sysinfo_t *sysinfo)
|
|||
printk(BIOS_SPEW, "GMCH supports DDR3 with %d MT or less\n", sysinfo->max_ddr3_mt);
|
||||
}
|
||||
|
||||
const unsigned max_fsb = (capid >> 28) & 0x3;
|
||||
const unsigned int max_fsb = (capid >> 28) & 0x3;
|
||||
switch (max_fsb) {
|
||||
case 1:
|
||||
sysinfo->max_fsb_mhz = 1067;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
typedef struct {
|
||||
u32 addr[RANKS_PER_CHANNEL];
|
||||
unsigned count;
|
||||
unsigned int count;
|
||||
} address_bunch_t;
|
||||
|
||||
/* Read Training. */
|
||||
|
|
|
|||
|
|
@ -205,7 +205,7 @@ static inline void gtt_write_regs(const struct gt_reg *gt)
|
|||
#define GTT_RETRY 1000
|
||||
int gtt_poll(u32 reg, u32 mask, u32 value)
|
||||
{
|
||||
unsigned try = GTT_RETRY;
|
||||
unsigned int try = GTT_RETRY;
|
||||
u32 data;
|
||||
|
||||
while (try--) {
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ void dump_spd_registers(void)
|
|||
int i;
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
for (i = 0; i < DIMM_SOCKETS; i++) {
|
||||
unsigned device;
|
||||
unsigned int device;
|
||||
device = DIMM0 + i;
|
||||
if (device) {
|
||||
int j;
|
||||
|
|
@ -45,7 +45,7 @@ void dump_spd_registers(void)
|
|||
}
|
||||
}
|
||||
|
||||
void dump_pci_device(unsigned dev)
|
||||
void dump_pci_device(unsigned int dev)
|
||||
{
|
||||
int i;
|
||||
printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ void sdram_initialize(void);
|
|||
/* Debug */
|
||||
#if CONFIG(DEBUG_RAM_SETUP)
|
||||
void dump_spd_registers(void);
|
||||
void dump_pci_device(unsigned dev);
|
||||
void dump_pci_device(unsigned int dev);
|
||||
#else
|
||||
#define dump_spd_registers()
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ void gtt_write(u32 reg, u32 data)
|
|||
#define GTT_RETRY 1000
|
||||
int gtt_poll(u32 reg, u32 mask, u32 value)
|
||||
{
|
||||
unsigned try = GTT_RETRY;
|
||||
unsigned int try = GTT_RETRY;
|
||||
u32 data;
|
||||
|
||||
while (try--) {
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ static void mc_read_resources(struct device *dev)
|
|||
D0F0_TOUUD);
|
||||
|
||||
printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base);
|
||||
printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned)TOUUD);
|
||||
printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)TOUUD);
|
||||
|
||||
/* Report the memory regions */
|
||||
ram_resource(dev, 3, 0, 640);
|
||||
|
|
|
|||
|
|
@ -207,13 +207,13 @@ struct raminfo {
|
|||
u8 mode4030[2];
|
||||
u16 avg4044[2];
|
||||
u16 max4048[2];
|
||||
unsigned total_memory_mb;
|
||||
unsigned interleaved_part_mb;
|
||||
unsigned non_interleaved_part_mb;
|
||||
unsigned int total_memory_mb;
|
||||
unsigned int interleaved_part_mb;
|
||||
unsigned int non_interleaved_part_mb;
|
||||
|
||||
u32 heci_bar;
|
||||
u64 heci_uma_addr;
|
||||
unsigned memory_reserved_for_heci_mb;
|
||||
unsigned int memory_reserved_for_heci_mb;
|
||||
|
||||
struct ram_training training;
|
||||
u32 last_500_command[2];
|
||||
|
|
@ -549,14 +549,14 @@ enum {
|
|||
|
||||
static void calculate_timings(struct raminfo *info)
|
||||
{
|
||||
unsigned cycletime;
|
||||
unsigned cas_latency_time;
|
||||
unsigned supported_cas_latencies;
|
||||
unsigned channel, slot;
|
||||
unsigned clock_speed_index;
|
||||
unsigned min_cas_latency;
|
||||
unsigned cas_latency;
|
||||
unsigned max_clock_index;
|
||||
unsigned int cycletime;
|
||||
unsigned int cas_latency_time;
|
||||
unsigned int supported_cas_latencies;
|
||||
unsigned int channel, slot;
|
||||
unsigned int clock_speed_index;
|
||||
unsigned int min_cas_latency;
|
||||
unsigned int cas_latency;
|
||||
unsigned int max_clock_index;
|
||||
|
||||
/* Find common CAS latency */
|
||||
supported_cas_latencies = 0x3fe;
|
||||
|
|
@ -579,7 +579,7 @@ static void calculate_timings(struct raminfo *info)
|
|||
for (channel = 0; channel < NUM_CHANNELS; channel++)
|
||||
for (slot = 0; slot < NUM_SLOTS; slot++)
|
||||
if (info->populated_ranks[channel][slot][0]) {
|
||||
unsigned timebase;
|
||||
unsigned int timebase;
|
||||
timebase =
|
||||
1000 *
|
||||
info->
|
||||
|
|
@ -627,9 +627,9 @@ static void calculate_timings(struct raminfo *info)
|
|||
|
||||
static void program_base_timings(struct raminfo *info)
|
||||
{
|
||||
unsigned channel;
|
||||
unsigned slot, rank, lane;
|
||||
unsigned extended_silicon_revision;
|
||||
unsigned int channel;
|
||||
unsigned int slot, rank, lane;
|
||||
unsigned int extended_silicon_revision;
|
||||
int i;
|
||||
|
||||
extended_silicon_revision = info->silicon_revision;
|
||||
|
|
@ -790,30 +790,30 @@ static unsigned int cycle_ps(struct raminfo *info)
|
|||
}
|
||||
|
||||
/* Frequency in 1.(1)=10/9 MHz units. */
|
||||
static unsigned frequency_11(struct raminfo *info)
|
||||
static unsigned int frequency_11(struct raminfo *info)
|
||||
{
|
||||
return (info->clock_speed_index + 3) * 120;
|
||||
}
|
||||
|
||||
/* Frequency in 0.1 MHz units. */
|
||||
static unsigned frequency_01(struct raminfo *info)
|
||||
static unsigned int frequency_01(struct raminfo *info)
|
||||
{
|
||||
return 100 * frequency_11(info) / 9;
|
||||
}
|
||||
|
||||
static unsigned ps_to_halfcycles(struct raminfo *info, unsigned int ps)
|
||||
static unsigned int ps_to_halfcycles(struct raminfo *info, unsigned int ps)
|
||||
{
|
||||
return (frequency_11(info) * 2) * ps / 900000;
|
||||
}
|
||||
|
||||
static unsigned ns_to_cycles(struct raminfo *info, unsigned int ns)
|
||||
static unsigned int ns_to_cycles(struct raminfo *info, unsigned int ns)
|
||||
{
|
||||
return (frequency_11(info)) * ns / 900;
|
||||
}
|
||||
|
||||
static void compute_derived_timings(struct raminfo *info)
|
||||
{
|
||||
unsigned channel, slot, rank;
|
||||
unsigned int channel, slot, rank;
|
||||
int extended_silicon_revision;
|
||||
int some_delay_1_ps;
|
||||
int some_delay_2_ps;
|
||||
|
|
@ -1157,7 +1157,7 @@ static void jedec_init(struct raminfo *info)
|
|||
|
||||
static void program_modules_memory_map(struct raminfo *info, int pre_jedec)
|
||||
{
|
||||
unsigned channel, slot, rank;
|
||||
unsigned int channel, slot, rank;
|
||||
unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */
|
||||
unsigned int channel_0_non_interleaved;
|
||||
|
||||
|
|
@ -1196,7 +1196,7 @@ static void program_board_delay(struct raminfo *info)
|
|||
int some_delay_ns;
|
||||
int some_delay_3_half_cycles;
|
||||
|
||||
unsigned channel, i;
|
||||
unsigned int channel, i;
|
||||
int high_multiplier;
|
||||
int lane_3_delay;
|
||||
int cas_latency_derived;
|
||||
|
|
@ -1234,7 +1234,7 @@ static void program_board_delay(struct raminfo *info)
|
|||
MCHBAR16(0x125) = 0x1360;
|
||||
MCHBAR8(0x127) = 0x40;
|
||||
if (info->fsb_frequency < frequency_11(info) / 2) {
|
||||
unsigned some_delay_2_half_cycles;
|
||||
unsigned int some_delay_2_half_cycles;
|
||||
high_multiplier = 1;
|
||||
some_delay_2_half_cycles = ps_to_halfcycles(info,
|
||||
((3 *
|
||||
|
|
@ -1487,7 +1487,7 @@ static void collect_system_info(struct raminfo *info)
|
|||
{
|
||||
u32 capid0[3];
|
||||
int i;
|
||||
unsigned channel;
|
||||
unsigned int channel;
|
||||
|
||||
/* Wait for some bit, maybe TXT clear. */
|
||||
while (!(read8((u8 *)0xfed40000) & (1 << 7)))
|
||||
|
|
@ -3204,9 +3204,9 @@ static void ram_training(struct raminfo *info)
|
|||
MCHBAR16(0xfc4) = saved_fc4;
|
||||
}
|
||||
|
||||
static unsigned gcd(unsigned a, unsigned b)
|
||||
static unsigned int gcd(unsigned int a, unsigned int b)
|
||||
{
|
||||
unsigned t;
|
||||
unsigned int t;
|
||||
if (a > b) {
|
||||
t = a;
|
||||
a = b;
|
||||
|
|
@ -3226,7 +3226,7 @@ static inline int div_roundup(int a, int b)
|
|||
return DIV_ROUND_UP(a, b);
|
||||
}
|
||||
|
||||
static unsigned lcm(unsigned a, unsigned b)
|
||||
static unsigned int lcm(unsigned int a, unsigned int b)
|
||||
{
|
||||
return (a * b) / gcd(a, b);
|
||||
}
|
||||
|
|
@ -3723,7 +3723,7 @@ void chipset_init(const int s3resume)
|
|||
|
||||
void raminit(const int s3resume, const u8 *spd_addrmap)
|
||||
{
|
||||
unsigned channel, slot, lane, rank;
|
||||
unsigned int channel, slot, lane, rank;
|
||||
int i;
|
||||
struct raminfo info;
|
||||
u8 x2ca8;
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ static inline uint8_t vbnv_data(int index)
|
|||
/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. */
|
||||
static uint8_t crc8_vbnv(const uint8_t *data, int len)
|
||||
{
|
||||
unsigned crc = 0;
|
||||
unsigned int crc = 0;
|
||||
int i, j;
|
||||
|
||||
for (j = len; j; j--, data++) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue