timestamp,vc/google/chromeos/cr50: Add timestamp for enable update
cr50_enable_update takes a non-trivial amount of time. TEST=Boot guybrush and dump timestamps 553:started TPM enable update 3,615,156 (444) 554:finished TPM enable update 3,632,810 (17,654) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I522d0638a4a6ae9624965e49b47bca8743c3206c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -77,6 +77,8 @@ enum timestamp_id {
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TS_START_COPYVPD = 550,
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TS_START_COPYVPD = 550,
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TS_END_COPYVPD_RO = 551,
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TS_END_COPYVPD_RO = 551,
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TS_END_COPYVPD_RW = 552,
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TS_END_COPYVPD_RW = 552,
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TS_START_TPM_ENABLE_UPDATE = 553,
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TS_END_TPM_ENABLE_UPDATE = 554,
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/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
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/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
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TS_AGESA_INIT_RESET_START = 900,
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TS_AGESA_INIT_RESET_START = 900,
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@ -204,6 +206,8 @@ static const struct timestamp_id_to_name {
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{ TS_END_TPMPCR, "finished TPM PCR extend" },
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{ TS_END_TPMPCR, "finished TPM PCR extend" },
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{ TS_START_TPMLOCK, "starting locking TPM" },
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{ TS_START_TPMLOCK, "starting locking TPM" },
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{ TS_END_TPMLOCK, "finished locking TPM" },
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{ TS_END_TPMLOCK, "finished locking TPM" },
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{ TS_START_TPM_ENABLE_UPDATE, "started TPM enable update" },
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{ TS_END_TPM_ENABLE_UPDATE, "finished TPM enable update" },
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{ TS_START_COPYVPD, "starting to load Chrome OS VPD" },
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{ TS_START_COPYVPD, "starting to load Chrome OS VPD" },
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{ TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" },
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{ TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" },
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@ -9,6 +9,7 @@
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#include <vb2_api.h>
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#include <vb2_api.h>
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#include <security/vboot/vboot_common.h>
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#include <security/vboot/vboot_common.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <timestamp.h>
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#define CR50_RESET_DELAY_MS 1000
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#define CR50_RESET_DELAY_MS 1000
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@ -89,6 +90,8 @@ static void enable_update(void *unused)
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return;
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return;
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}
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}
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timestamp_add_now(TS_START_TPM_ENABLE_UPDATE);
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/* Reboot in 1000 ms if necessary. */
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/* Reboot in 1000 ms if necessary. */
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ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS,
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ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS,
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&num_restored_headers);
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&num_restored_headers);
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@ -115,8 +118,10 @@ static void enable_update(void *unused)
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* If the Cr50 doesn't requires a reset, continue booting.
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* If the Cr50 doesn't requires a reset, continue booting.
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*/
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*/
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cr50_reset_reqd = cr50_is_reset_needed();
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cr50_reset_reqd = cr50_is_reset_needed();
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if (!cr50_reset_reqd)
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if (!cr50_reset_reqd) {
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timestamp_add_now(TS_END_TPM_ENABLE_UPDATE);
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return;
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return;
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}
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printk(BIOS_INFO, "Waiting for CR50 reset to enable TPM.\n");
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printk(BIOS_INFO, "Waiting for CR50 reset to enable TPM.\n");
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elog_add_event(ELOG_TYPE_CR50_NEED_RESET);
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elog_add_event(ELOG_TYPE_CR50_NEED_RESET);
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