diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 8a1116a2d6..0e3d365ae9 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -32,8 +32,6 @@
 #define HDA_ICII_BUSY (1 << 0)
 #define HDA_ICII_VALID (1 << 1)
 
-typedef struct southbridge_intel_bd82x6x_config config_t;
-
 static int set_bits(u32 port, u32 mask, u32 val)
 {
 	u32 reg32;
diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h
index 828466c0c4..466ae79b46 100644
--- a/src/southbridge/intel/ibexpeak/chip.h
+++ b/src/southbridge/intel/ibexpeak/chip.h
@@ -17,87 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
-#define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
+#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H
+#define SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H
 
-struct southbridge_intel_bd82x6x_config {
-	/**
-	 * Interrupt Routing configuration
-	 * If bit7 is 1, the interrupt is disabled.
-	 */
-	uint8_t pirqa_routing;
-	uint8_t pirqb_routing;
-	uint8_t pirqc_routing;
-	uint8_t pirqd_routing;
-	uint8_t pirqe_routing;
-	uint8_t pirqf_routing;
-	uint8_t pirqg_routing;
-	uint8_t pirqh_routing;
+#define southbridge_intel_bd82x6x_config southbridge_intel_ibexpeak_config
 
-	/**
-	 * GPI Routing configuration
-	 *
-	 * Only the lower two bits have a meaning:
-	 * 00: No effect
-	 * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
-	 * 10: SCI (if corresponding GPIO_EN bit is also set)
-	 * 11: reserved
-	 */
-	uint8_t gpi0_routing;
-	uint8_t gpi1_routing;
-	uint8_t gpi2_routing;
-	uint8_t gpi3_routing;
-	uint8_t gpi4_routing;
-	uint8_t gpi5_routing;
-	uint8_t gpi6_routing;
-	uint8_t gpi7_routing;
-	uint8_t gpi8_routing;
-	uint8_t gpi9_routing;
-	uint8_t gpi10_routing;
-	uint8_t gpi11_routing;
-	uint8_t gpi12_routing;
-	uint8_t gpi13_routing;
-	uint8_t gpi14_routing;
-	uint8_t gpi15_routing;
+#include "../bd82x6x/chip.h"
 
-	uint32_t gpe0_en;
-	uint16_t alt_gp_smi_en;
-
-	/* IDE configuration */
-	uint32_t ide_legacy_combined;
-	uint32_t sata_ahci;
-	uint8_t sata_port_map;
-	uint32_t sata_port0_gen3_tx;
-	uint32_t sata_port1_gen3_tx;
-
-	/**
-	 * SATA Interface Speed Support Configuration
-	 *
-	 * Only the lower two bits have a meaning:
-	 * 00 - No effect (leave as chip default)
-	 * 01 - 1.5 Gb/s maximum speed
-	 * 10 - 3.0 Gb/s maximum speed
-	 * 11 - 6.0 Gb/s maximum speed
-	 */
-	uint8_t sata_interface_speed_support;
-
-	uint32_t gen1_dec;
-	uint32_t gen2_dec;
-	uint32_t gen3_dec;
-	uint32_t gen4_dec;
-
-	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
-
-	/* Override PCIe ASPM */
-	uint8_t pcie_aspm_f0;
-	uint8_t pcie_aspm_f1;
-	uint8_t pcie_aspm_f2;
-	uint8_t pcie_aspm_f3;
-	uint8_t pcie_aspm_f4;
-	uint8_t pcie_aspm_f5;
-	uint8_t pcie_aspm_f6;
-	uint8_t pcie_aspm_f7;
-};
-
-#endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
+#endif
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 8417a90cdf..691b1393b5 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -38,7 +38,7 @@
 #define ENABLE_ACPI_MODE_IN_COREBOOT	0
 #define TEST_SMM_FLASH_LOCKDOWN		0
 
-typedef struct southbridge_intel_bd82x6x_config config_t;
+typedef struct southbridge_intel_ibexpeak_config config_t;
 
 /**
  * Set miscellanous static southbridge features.
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 943d0854a9..9f96d49cf7 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -26,7 +26,7 @@
 #include <device/pci_ids.h>
 #include "pch.h"
 
-typedef struct southbridge_intel_bd82x6x_config config_t;
+typedef struct southbridge_intel_ibexpeak_config config_t;
 
 static inline u32 sir_read(struct device *dev, int idx)
 {