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rambi: Add ACPI devices and interrupts for codec and ALS 

The Codec and ALS both have interrupt sources that can be configured.
The ALS kernel driver currently does not try to use it but the codec
driver does for things like jack detect.

ACPI Devices are added, but as with other ACPI devices the HID may
need to be updated once more official strings are decided.

BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual: build and boot on rambi and check for functional lightsensor

Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182366
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5049
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Duncan Laurie 2014-01-13 16:37:51 -08:00 committed by Kyösti Mälkki
parent 59d1d87c86
commit 469b5205c3
4 changed files with 93 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
src/mainboard/google/rambi/acpi/mainboard.asl
View File

@ -205,6 +205,86 @@ Scope (\_SB.I2C1)
}
}
Scope (\_SB.I2C2)
{
Device (CODC)
{
/*
* TODO(dlaurie): Need official HID.
*
* The current HID is created from the Maxim Integrated
* PCI Vendor ID 193Ch and a shortened device identifier.
*/
Name (_HID, "193C9890")
Name (_DDN, "Maxim 98090 Codec")
Name (_UID, 1)
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x10, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\_SB.I2C2", // ResourceSource
)
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_CODEC_IRQ
}
})
Method (_STA)
{
If (LEqual (\S2EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
}
}
Scope (\_SB.I2C5)
{
Device (ALSI)
{
/*
* TODO(dlaurie): Need official HID.
*
* The current HID is created from the Intersil PNP
* Vendor ID "LSD" and a shortened device identifier.
*/
Name (_HID, EisaId ("LSD2918"))
Name (_DDN, "Intersil 29018 Ambient Light Sensor")
Name (_UID, 1)
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x44, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\_SB.I2C5", // ResourceSource
)
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_ALS_IRQ
}
})
Method (_STA)
{
If (LEqual (\S5EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
}
}
Scope (\_SB.I2C6)
{
Device (ATSB)

6
src/mainboard/google/rambi/gpio.c
View File

@ -126,7 +126,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = {
GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */
GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */
GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */
GPIO_INPUT, /* S0-SC070 - ALS_INT_L - INT */
GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */
GPIO_NC, /* S0-SC071 - NC */
GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */
GPIO_NC, /* S0-SC073 - NC */
@ -172,7 +172,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */
GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */
GPIO_NC, /* S508 - NC */
GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */
GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */
GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */
GPIO_FUNC0, /* S511 - SUSPWRDNACK */
GPIO_FUNC0, /* S512 - WIFI_SUSCLK */
@ -214,9 +214,11 @@ static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
[ALS_IRQ_OFFSET] = ALS_IRQ_GPIO,
};
static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
};
static struct soc_gpio_config gpio_config = {

7
src/mainboard/google/rambi/irqroute.h
View File

@ -50,7 +50,14 @@
#define TPAD_IRQ_OFFSET 0
#define TOUCH_IRQ_OFFSET 1
#define I8042_IRQ_OFFSET 2
#define ALS_IRQ_OFFSET 3
/* Corresponding SCORE GPIO pins */
#define TPAD_IRQ_GPIO 55
#define TOUCH_IRQ_GPIO 72
#define I8042_IRQ_GPIO 101
#define ALS_IRQ_GPIO 70
/* SUS bank DIRQs - up to 16 supported */
#define CODEC_IRQ_OFFSET 0
/* Corresponding SUS GPIO pins */
#define CODEC_IRQ_GPIO 9

2
src/mainboard/google/rambi/onboard.h
View File

@ -35,5 +35,7 @@
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
#endif