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make quartet compile. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2003-11-04 11:57:10 +00:00
parent ab5ab6e556
commit 469bd43194
2 changed files with 18 additions and 16 deletions
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6
src/mainboard/amd/quartet/Config.lb
View File

@ -230,7 +230,7 @@ northbridge amd/amdk8 "mc0"
pci 0:18.2
pci 0:18.3
southbridge amd/amd8111 "amd8111" link 2
pci 0:0.0 on
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
@ -266,13 +266,13 @@ northbridge amd/amdk8 "mc1"
pci 0:19.1
pci 0:19.2
pci 0:19.3
southbridge amd/amd8131 "amd8131" link 1
southbridge amd/amd8131 "amd8131_0" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8131 "amd8131" link 1
southbridge amd/amd8131 "amd8131_1" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0

28
src/mainboard/amd/quartet/auto.c
View File

@ -1,6 +1,6 @@
#define ASSEMBLY 1
#define MAXIMUM_CONSOLE_LOGLEVEL 9
#define DEFAULT_CONSOLE_LOGLEVEL 9
// #define MAXIMUM_CONSOLE_LOGLEVEL 9
// #define DEFAULT_CONSOLE_LOGLEVEL 9
#include <stdint.h>
#include <device/pci_def.h>
@ -100,16 +100,18 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
return ret;
}
static inline int spd_read_byte(unsigned device, unsigned address)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x30
unsigned hub = device >> 8;
device &= 0xff;
smbus_write_byte(SMBUS_HUB, 0x01, 1<<hub);
smbus_write_byte(SMBUS_HUB, 0x03, 0);
unsigned device=(ctrl->channel0[0])>>8;
smbus_write_byte(SMBUS_HUB | (0x01<<8), device);
smbus_write_byte(SMBUS_HUB | (0x03<<8), 0);
}
return smbus_read_byte(device, address);
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device & 0xff, address);
}
/* no specific code here. this should go away completely */
@ -181,10 +183,10 @@ static void pc87360_enable_serial(void)
pnp_set_iobase0(SIO_BASE, 0x3f8);
}
#define RC0 (0<<8)
#define RC1 (1<<8)
#define RC2 (2<<8)
#define RC3 (3<<8)
#define RC0 ((1<<0)<<8)
#define RC1 ((1<<1)<<8)
#define RC2 ((1<<2)<<8)
#define RC3 ((1<<3)<<8)
#define DIMM0 0xa0
#define DIMM1 0xa2