soc/intel/skylake: Use common systemagent code
This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
Martin Roth
parent
7609c654b1
commit
46a7178267
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@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS
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select RELOCATABLE_MODULES
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select RELOCATABLE_RAMSTAGE
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select RTC
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select SA_ENABLE_DPR
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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@ -19,38 +19,13 @@
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#define SOC_SKYLAKE_SYSTEMAGENT_H
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#define SA_IGD_OPROM_VENDEV 0x80860406
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/* Device 0:0.0 PCI configuration space */
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#define EPBAR 0x40
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define GGC 0x50 /* GMCH Graphics Control */
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D7EN (1 << 14)
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#define DEVEN_D4EN (1 << 7)
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#define DEVEN_D3EN (1 << 5)
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#define DEVEN_D2EN (1 << 4)
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#define DEVEN_D1F0EN (1 << 3)
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#define DEVEN_D1F1EN (1 << 2)
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#define DEVEN_D1F2EN (1 << 1)
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#define DEVEN_D0EN (1 << 0)
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#define DPR 0x5c
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#define DPR_EPM (1 << 2)
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#define DPR_PRS (1 << 1)
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#define DPR_SIZE_MASK 0xff0
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#define PAM0 0x80
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#define PAM1 0x81
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#define PAM2 0x82
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#define PAM3 0x83
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#define PAM4 0x84
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#define PAM5 0x85
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#define PAM6 0x86
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#define SMRAM 0x88 /* System Management RAM Control */
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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@ -58,23 +33,8 @@
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define MESEG_BASE 0x70 /* Management Engine Base. */
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#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
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#define REMAPBASE 0x90 /* Remap base. */
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#define REMAPLIMIT 0x98 /* Remap limit. */
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#define TOM 0xa0 /* Top of DRAM in memory controller space. */
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#define SKPAD 0xdc /* Scratchpad Data */
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/* MCHBAR */
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#define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x))
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#define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x))
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#define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x))
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#define MCHBAR_PEI_VERSION 0x5034
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#define BIOS_RESET_CPL 0x5da8
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#define EDRAMBAR 0x5408
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#define MCH_PAIR 0x5418
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#define GDXCBAR 0x5420
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#define MCH_PKG_POWER_LIMIT_LO 0x59a0
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@ -82,24 +42,6 @@
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#define MCH_DDR_POWER_LIMIT_LO 0x58e0
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#define MCH_DDR_POWER_LIMIT_HI 0x58e4
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/* PCODE MMIO communications live in the MCHBAR. */
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#define BIOS_MAILBOX_INTERFACE 0x5da4
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#define MAILBOX_RUN_BUSY (1 << 31)
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/* Errors are returned back in bits 7:0. */
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#define MAILBOX_BIOS_ERROR_NONE 0
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#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
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#define MAILBOX_BIOS_ERROR_TIMEOUT 2
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#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
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#define MAILBOX_BIOS_ERROR_RESERVED 4
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#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
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#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
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#define MAILBOX_BIOS_ERROR_VR_ERROR 7
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/* Data is passed through bits 31:0 of the data register. */
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#define BIOS_MAILBOX_DATA 0x5da0
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/* System Agent identification */
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u8 systemagent_revision(void);
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/* Top of 32bit usable memory */
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u32 top_of_32bit_ram(void);
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@ -15,38 +15,31 @@
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* GNU General Public License for more details.
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*/
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#include <stdlib.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <reg_script.h>
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#include <device/device.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/systemagent.h>
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static const struct reg_script systemagent_early_init_script[] = {
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REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1),
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REG_PCI_WRITE32(DMIBAR, DMI_BASE_ADDRESS | 1),
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REG_PCI_WRITE32(EPBAR, EP_BASE_ADDRESS | 1),
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REG_MMIO_WRITE32(MCH_BASE_ADDRESS + EDRAMBAR, EDRAM_BASE_ADDRESS | 1),
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REG_MMIO_WRITE32(MCH_BASE_ADDRESS + GDXCBAR, GDXC_BASE_ADDRESS | 1),
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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REG_PCI_WRITE8(PAM0, 0x30),
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REG_PCI_WRITE8(PAM1, 0x33),
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REG_PCI_WRITE8(PAM2, 0x33),
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REG_PCI_WRITE8(PAM3, 0x33),
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REG_PCI_WRITE8(PAM4, 0x33),
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REG_PCI_WRITE8(PAM5, 0x33),
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REG_PCI_WRITE8(PAM6, 0x33),
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/* Device enable: IGD and Mini-HD */
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REG_PCI_WRITE32(DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN),
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REG_SCRIPT_END
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};
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void systemagent_early_init(void)
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{
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reg_script_run_on_dev(SA_DEV_ROOT, systemagent_early_init_script);
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static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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};
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static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {
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{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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};
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/* Set Fixed MMIO addresss into PCI configuration space */
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sa_set_pci_bar(soc_fixed_pci_resources,
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ARRAY_SIZE(soc_fixed_pci_resources));
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/* Set Fixed MMIO addresss into MCH base address */
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sa_set_mch_bar(soc_fixed_mch_resources,
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ARRAY_SIZE(soc_fixed_mch_resources));
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/* Enable PAM regisers */
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enable_pam_region();
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}
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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* Copyright (C) 2015-2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,415 +16,49 @@
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*/
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <cbmem.h>
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#include <romstage_handoff.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <intelblocks/systemagent.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/systemagent.h>
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u8 systemagent_revision(void)
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Mmeory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
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}
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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};
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static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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{
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u32 pciexbar_reg;
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*base = 0;
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*len = 0;
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pciexbar_reg = pci_read_config32(dev, index);
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if (!(pciexbar_reg & (1 << 0)))
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return 0;
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: /* 256MB */
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*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
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(1 << 28));
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*len = 256 * 1024 * 1024;
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return 1;
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case 1: /* 128M */
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*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
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(1 << 28)|(1 << 27));
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*len = 128 * 1024 * 1024;
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return 1;
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case 2: /* 64M */
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*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
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(1 << 28)|(1 << 27)|(1 << 26));
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*len = 64 * 1024 * 1024;
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return 1;
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}
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return 0;
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}
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static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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{
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u32 bar;
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bar = pci_read_config32(dev, index);
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/* If not enabled don't report it. */
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if (!(bar & 0x1))
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return 0;
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/* Knock down the enable bit. */
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*base = bar & ~1;
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return 1;
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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}
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/*
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* There are special BARs that actually are programmed in the MCHBAR. These
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* Intel special features, but they do consume resources that need to be
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* accounted for.
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* SoC implementation
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*
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* Perform System Agent Initialization during Ramstage phase.
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*/
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static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
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u32 *len)
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void soc_systemagent_init(struct device *dev)
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{
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u32 bar;
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bar = MCHBAR32(index);
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/* If not enabled don't report it. */
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if (!(bar & 0x1))
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return 0;
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/* Knock down the enable bit. */
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*base = bar & ~1;
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return 1;
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}
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struct fixed_mmio_descriptor {
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unsigned int index;
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u32 size;
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int (*get_resource)(device_t dev, unsigned int index,
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u32 *base, u32 *size);
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const char *description;
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};
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struct fixed_mmio_descriptor mc_fixed_resources[] = {
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{ PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" },
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{ MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" },
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{ DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" },
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{ EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" },
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{ GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" },
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{ EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
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};
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/*
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* Add all known fixed MMIO ranges that hang off the host bridge/memory
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* controller device.
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*/
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static void mc_add_fixed_mmio_resources(device_t dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
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u32 base;
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u32 size;
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struct resource *resource;
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unsigned int index;
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size = mc_fixed_resources[i].size;
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index = mc_fixed_resources[i].index;
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if (!mc_fixed_resources[i].get_resource(dev, index,
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&base, &size))
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continue;
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resource = new_resource(dev, mc_fixed_resources[i].index);
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resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
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IORESOURCE_STORED | IORESOURCE_RESERVE |
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IORESOURCE_ASSIGNED;
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resource->base = base;
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resource->size = size;
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printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
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__func__, mc_fixed_resources[i].description, index,
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(unsigned long)base, (unsigned long)(base + size - 1));
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}
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}
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struct map_entry {
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int reg;
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int is_64_bit;
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int is_limit;
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const char *description;
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};
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static void read_map_entry(device_t dev, struct map_entry *entry,
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uint64_t *result)
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{
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uint64_t value;
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uint64_t mask;
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/* All registers are on a 1MiB granularity. */
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mask = ((1ULL<<20)-1);
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mask = ~mask;
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value = 0;
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if (entry->is_64_bit) {
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value = pci_read_config32(dev, entry->reg + 4);
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value <<= 32;
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}
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value |= (uint64_t) pci_read_config32(dev, entry->reg);
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value &= mask;
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if (entry->is_limit)
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value |= ~mask;
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*result = value;
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}
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#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
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{ \
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.reg = reg_, \
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.is_64_bit = is_64_, \
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.is_limit = is_limit_, \
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.description = desc_, \
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}
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#define MAP_ENTRY_BASE_64(reg_, desc_) \
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MAP_ENTRY(reg_, 1, 0, desc_)
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#define MAP_ENTRY_LIMIT_64(reg_, desc_) \
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MAP_ENTRY(reg_, 1, 1, desc_)
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#define MAP_ENTRY_BASE_32(reg_, desc_) \
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MAP_ENTRY(reg_, 0, 0, desc_)
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enum {
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TOM_REG,
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TOUUD_REG,
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MESEG_BASE_REG,
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MESEG_LIMIT_REG,
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REMAP_BASE_REG,
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REMAP_LIMIT_REG,
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TOLUD_REG,
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BGSM_REG,
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BDSM_REG,
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TSEG_REG,
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/* Must be last. */
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NUM_MAP_ENTRIES
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};
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static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
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[TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
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[TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
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[MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
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[MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
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[REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
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[REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
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[TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
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[BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
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[BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
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[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
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};
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static void mc_read_map_entries(device_t dev, uint64_t *values)
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{
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int i;
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for (i = 0; i < NUM_MAP_ENTRIES; i++)
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read_map_entry(dev, &memory_map[i], &values[i]);
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}
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static void mc_report_map_entries(device_t dev, uint64_t *values)
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{
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int i;
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for (i = 0; i < NUM_MAP_ENTRIES; i++) {
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printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
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memory_map[i].description, values[i]);
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}
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/* One can validate the BDSM and BGSM against the GGC. */
|
||||
printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
|
||||
}
|
||||
|
||||
static void mc_add_dram_resources(device_t dev)
|
||||
{
|
||||
unsigned long base_k, size_k;
|
||||
unsigned long touud_k;
|
||||
unsigned long index;
|
||||
struct resource *resource;
|
||||
uint64_t mc_values[NUM_MAP_ENTRIES];
|
||||
unsigned long dpr_size = 0;
|
||||
u32 dpr_reg;
|
||||
|
||||
/* Read in the MAP registers and report their values. */
|
||||
mc_read_map_entries(dev, &mc_values[0]);
|
||||
mc_report_map_entries(dev, &mc_values[0]);
|
||||
|
||||
/*
|
||||
* DMA Protected Range can be reserved below TSEG for PCODE patch
|
||||
* or TXT/BootGuard related data. Rather than report a base address
|
||||
* the DPR register reports the TOP of the region, which is the same
|
||||
* as TSEG base. The region size is reported in MiB in bits 11:4.
|
||||
*/
|
||||
dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);
|
||||
if (dpr_reg & DPR_EPM) {
|
||||
dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16;
|
||||
printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);
|
||||
}
|
||||
|
||||
/*
|
||||
* These are the host memory ranges that should be added:
|
||||
* - 0 -> 0xa0000: cacheable
|
||||
* - 0xc0000 -> top_of_ram : cacheable
|
||||
* - top_of_ram -> TSEG - DPR: uncacheable
|
||||
* - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved
|
||||
* - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
|
||||
* - 4GiB -> TOUUD: cacheable
|
||||
*
|
||||
* The default SMRAM space is reserved so that the range doesn't
|
||||
* have to be saved during S3 Resume. Once marked reserved the OS
|
||||
* cannot use the memory. This is a bit of an odd place to reserve
|
||||
* the region, but the CPU devices don't have dev_ops->read_resources()
|
||||
* called on them.
|
||||
*
|
||||
* The range 0xa0000 -> 0xc0000 does not have any resources
|
||||
* associated with it to handle legacy VGA memory. If this range
|
||||
* is not omitted the mtrr code will setup the area as cacheable
|
||||
* causing VGA access to not work.
|
||||
*
|
||||
* The TSEG region is mapped as cacheable so that one can perform
|
||||
* SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
|
||||
* precedence over the existing MTRRs covering this region.
|
||||
*
|
||||
* It should be noted that cacheable entry types need to be added in
|
||||
* order. The reason is that the current MTRR code assumes this and
|
||||
* falls over itself if it isn't.
|
||||
*
|
||||
* The resource index starts low and should not meet or exceed
|
||||
* PCI_BASE_ADDRESS_0.
|
||||
*/
|
||||
index = 0;
|
||||
|
||||
/* 0 - > 0xa0000 */
|
||||
base_k = 0;
|
||||
size_k = (0xa0000 >> 10) - base_k;
|
||||
ram_resource(dev, index++, base_k, size_k);
|
||||
|
||||
/* 0xc0000 -> top_of_ram */
|
||||
base_k = 0xc0000 >> 10;
|
||||
size_k = (top_of_32bit_ram() >> 10) - base_k;
|
||||
ram_resource(dev, index++, base_k, size_k);
|
||||
|
||||
/* top_of_ram -> TSEG - DPR */
|
||||
resource = new_resource(dev, index++);
|
||||
resource->base = top_of_32bit_ram();
|
||||
resource->size = mc_values[TSEG_REG] - dpr_size - resource->base;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
|
||||
IORESOURCE_STORED | IORESOURCE_RESERVE |
|
||||
IORESOURCE_ASSIGNED;
|
||||
|
||||
/* TSEG - DPR -> BGSM */
|
||||
resource = new_resource(dev, index++);
|
||||
resource->base = mc_values[TSEG_REG] - dpr_size;
|
||||
resource->size = mc_values[BGSM_REG] - resource->base;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
|
||||
IORESOURCE_STORED | IORESOURCE_RESERVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
|
||||
|
||||
/* BGSM -> TOLUD */
|
||||
resource = new_resource(dev, index++);
|
||||
resource->base = mc_values[BGSM_REG];
|
||||
resource->size = mc_values[TOLUD_REG] - resource->base;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
|
||||
IORESOURCE_STORED | IORESOURCE_RESERVE |
|
||||
IORESOURCE_ASSIGNED;
|
||||
|
||||
/* 4GiB -> TOUUD */
|
||||
base_k = 4096 * 1024; /* 4GiB */
|
||||
touud_k = mc_values[TOUUD_REG] >> 10;
|
||||
size_k = touud_k - base_k;
|
||||
if (touud_k > base_k)
|
||||
ram_resource(dev, index++, base_k, size_k);
|
||||
|
||||
/*
|
||||
* Reserve everything between A segment and 1MB:
|
||||
*
|
||||
* 0xa0000 - 0xbffff: legacy VGA
|
||||
* 0xc0000 - 0xfffff: RAM
|
||||
*/
|
||||
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
|
||||
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
|
||||
(0x100000 - 0xc0000) >> 10);
|
||||
|
||||
chromeos_reserve_ram_oops(dev, index++);
|
||||
}
|
||||
|
||||
static void systemagent_read_resources(device_t dev)
|
||||
{
|
||||
/* Read standard PCI resources. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Add all fixed MMIO resources. */
|
||||
mc_add_fixed_mmio_resources(dev);
|
||||
|
||||
/* Calculate and add DRAM resources. */
|
||||
mc_add_dram_resources(dev);
|
||||
}
|
||||
|
||||
static void systemagent_init(struct device *dev)
|
||||
{
|
||||
u8 bios_reset_cpl, pair;
|
||||
|
||||
/* Enable Power Aware Interrupt Routing */
|
||||
pair = MCHBAR8(MCH_PAIR);
|
||||
pair &= ~0x7; /* Clear 2:0 */
|
||||
pair |= 0x4; /* Fixed Priority */
|
||||
MCHBAR8(MCH_PAIR) = pair;
|
||||
enable_power_aware_intr();
|
||||
|
||||
/*
|
||||
* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
|
||||
* that BIOS has initialized memory and power management
|
||||
*/
|
||||
bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
|
||||
bios_reset_cpl |= 3;
|
||||
MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
|
||||
printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
|
||||
/* Enable BIOS Reset CPL */
|
||||
enable_bios_reset_cpl();
|
||||
|
||||
/* Configure turbo power limits 1ms after reset complete bit */
|
||||
mdelay(1);
|
||||
set_power_limits(28);
|
||||
}
|
||||
|
||||
static struct device_operations systemagent_ops = {
|
||||
.read_resources = &systemagent_read_resources,
|
||||
.set_resources = &pci_dev_set_resources,
|
||||
.enable_resources = &pci_dev_enable_resources,
|
||||
.init = &systemagent_init,
|
||||
.ops_pci = &soc_pci_ops,
|
||||
};
|
||||
|
||||
static const unsigned short systemagent_ids[] = {
|
||||
PCI_DEVICE_ID_INTEL_SKL_ID_U,
|
||||
PCI_DEVICE_ID_INTEL_SKL_ID_Y,
|
||||
PCI_DEVICE_ID_INTEL_SKL_ID_ULX,
|
||||
PCI_DEVICE_ID_INTEL_SKL_ID_H,
|
||||
PCI_DEVICE_ID_INTEL_SKL_ID_H_EM,
|
||||
PCI_DEVICE_ID_INTEL_KBL_ID_U,
|
||||
PCI_DEVICE_ID_INTEL_KBL_ID_Y,
|
||||
PCI_DEVICE_ID_INTEL_KBL_ID_H,
|
||||
PCI_DEVICE_ID_INTEL_KBL_U_R,
|
||||
0
|
||||
};
|
||||
|
||||
static const struct pci_driver systemagent_driver __pci_driver = {
|
||||
.ops = &systemagent_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.devices = systemagent_ids
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue