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mb/google/hatch/variants/helios: Modify touchscreen power on sequence 

The previous values do not affect the touchscreen function.  But, the
previous values cause the power leakage in S0ix.

from b/142368161:

1. Modify GPP_D: The specification define T1 >= 10ms. We change it to
   12ms for a safety and low impact value in our mind.  Enable pin as
   GPP_D9 is define to be AVDD in specification. Set it to 10ms to
   make it to be the final one to pull low during power off sequence .

2. Add GPP_C4: If we set stop_off_delay_ms to be 1.  The true T4 we
   got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be
   500us . So we change it to 5 to be a low impact value in our mind
   according to the true T4 value we got .

BUG=b:142368161
BRANCH=Master
TEST=emerge-hatch coreboot chromeos-bootimage
     ./util/abuild/abuild -p none -t google/hatch -x -a

Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kane Chen 2019-10-09 18:07:02 +08:00 committed by Shelley Chen
parent 2d90cb1547
commit 46b125ab6b
1 changed files with 6 additions and 2 deletions
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8
src/mainboard/google/hatch/variants/helios/overridetree.cb
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@ -107,9 +107,13 @@ chip soc/intel/cannonlake
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
register "generic.enable_delay_ms" = "10"
register "generic.enable_off_delay_ms" = "1"
register "generic.enable_delay_ms" = "12"
register "generic.enable_off_delay_ms" = "10"
register "generic.has_power_resource" = "1"
register "generic.stop_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
register "generic.stop_delay_ms" = "15"
register "generic.stop_off_delay_ms" = "5"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
end