spd: Add module voltage for 1.8V
Add SSTL 1.8 V Interface Level as specified in JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10. Change-Id: I0112a85f557826b629109e212dbbc752aeda305d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -125,6 +125,7 @@ enum spd_memory_type {
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#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */
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#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */
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#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */
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#define SPD_VOLTAGE_SSTL1 5 /* SSTL 1.8 */
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/* SPD_DIMM_CONFIG_TYPE values. */
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#define ERROR_SCHEME_NONE 0
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