From 46c5807d29a1fae542d22c82f6c07955f0296f78 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Sun, 28 Apr 2019 18:17:17 +0200
Subject: [PATCH] sb/intel/bd82x6x: Use system_reset()

Use already defined system_reset() function.

Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/southbridge/intel/bd82x6x/early_me.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index edb514bda7..f82ed3e979 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <device/pci_ops.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/pci_def.h>
@@ -179,8 +180,7 @@ int intel_early_me_init_done(u8 status)
 			reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
 			pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
 			set_global_reset(0);
-			outb(0x6, 0xcf9);
-			halt();
+			system_reset();
 		}
 
 		if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {