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intel/skylake: support 32bit uart8250_mem driver in romstage 

This patch adds 32bit uart8250_mem functionality in romstage
console for arch/x86.

BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for sklrvp; verified romstage logs on RVP3 board.

Change-Id: I6f13216b7f5ba8de48c781cd1791d0fa7ae0d921
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a17efdeec5524cbfc78015c358d1cf4f67485765
Original-Change-Id: I8b4e44c59bfd609a06807243df338763054b5865
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/271800
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10999
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Naveen Krishna Chatradhi 2015-05-18 21:25:52 +05:30 committed by Patrick Georgi
parent a73408d608
commit 46ca690ec0
1 changed files with 3 additions and 2 deletions
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5
src/soc/intel/skylake/romstage/uart.c
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@ -57,8 +57,9 @@ void pch_uart_init(void)
write32(base + SIO_REG_PPR_CLOCK, tmp); write32(base + SIO_REG_PPR_CLOCK, tmp);
/* Put UART2 in byte access mode for 16550 compatibility */ /* Put UART2 in byte access mode for 16550 compatibility */
pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32))
SIO_PCH_LEGACY_UART2); pcr_andthenor32(PID_SERIALIO,
R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2);
/* Configure GPIO for UART2 in native mode*/ /* Configure GPIO for UART2 in native mode*/
uartgpioinit(FALSE); uartgpioinit(FALSE);